Architectures for Stereo Vision - Signal Processing Systems - page 494

Fig. 13 Synchronized and
parallel calculation of the
path costs of the four paths
L 0 ◦ , L 45 ◦ , L 90 ◦ and L 135 ◦ for
the two pixels p 1 =[ x , y ] and

p 2 . Each delay

element stores the respective
path costs over all disparity
levels for the duration of one
processing step

=[ x − 2 , y + 1 ]

Generalization of this concept is only limited by the fact that the maximum angle
range must be within the half-closed interval 180 ◦ )

. This means that no paths
in opposite directions can be directly supported without additional hardware. The
two-dimensional parallelization allows regular data accesses of the input images
and all intermediate values and will further be referred to as row parallelism.
Moreover, this concept is independent of the processing method of the disparity
levels, which can be either serial or parallel. Processing the disparity levels in
parallel establishes a third dimension of parallelism, which will be referred to as
disparity level parallelism. An approach of particular interest for dedicated hardware
implementations is not to choose either extreme (none or all disparity levels in
parallel) but to process the disparity levels in small groups (e.g. 2, 4, or 8). In this
case the size of the path cost buffers, as specified above, remains constant while
the throughput increases linearly with the number of parallelized disparity levels.
However, some additional logic for the arithmetic computation of n paths in parallel
will be required. The increase of logic requirements vs. performance of disparity
level parallelism and row level parallelism will be investigated in Sect. 3.7.3 .

[ 0 ,

3.7.2 Architecture

The hardware architecture for the entire stereo matching algorithm is given in
Fig. 14 . Computation of the rank transform of both images and calculation of the
data dependent penalty term P 2 is done in parallel and synchronously utilizing the
same data path.