Architectures for Stereo Vision - Signal Processing Systems - page 485

as basis of an entire stereo vision system on an FPGA. Another complete system
based on SAD (w/o CA) is presented in [ 91 ] . Census with aggregation cues from
the original and gradient images is investigated in [ 1 ] . Color SAD with a fuzzy
logic disparity selection has been proposed and implemented on an FPGA [ 26 ] .
Methods and architectures using adaptive support weights have been proposed in
[ 14 ] employing a census variant and in [ 89 ] employing an absolute differences
variant. In order to reduce the amount of data to be processed [ 88 ] works on sobel
filtered images, which goes into the direction of sparse matching.
In [ 60 ] , the architecture of [ 17 ] , which is based on a local, phase-based method,
is extended to large disparity ranges without significant additional hardware cost by
adapting an offset of the smaller disparity search window across multiple frames.
After large disparity changes, a latency of several frames occurs before correct
disparity information can be regained. A bio-inspired method based on gabor filters
is introduced in [ 18 ] .
Among the implementations of dynamic programming approaches a trellis-based
implementation, using a single interline consistency constraint has been investigated
[ 68 ] . A dynamic programming approach based on a maximum-likelihood method is
implemented in [ 78 ] achieving 64 fps at 640 480 px with 128 disparity levels. And

a symmetric dynamic programming variant, similar to the GPU implementation of
[ 48 ] , has been implemented on an FPGA [ 65 ] .
An FPGA architecture for memory efficient belief propagation for stereo match-
ing has been proposed in [ 71 ] . New concepts and architectures for the message
passing in BP are proposed [ 87 ] .
For semi-global matching two architectures have been proposed. The implemen-
tation of [ 25 ] utilizes a SGM variant with depth adaptive sub-sampling. It achieves
27 fps at 320

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200 px and 64 px disparity range. A parameterizable parallelization
scheme for SGM and a corresponding FPGA architecture have been proposed in
[ 7 , 8 ] . It achieves, depending on the degree of parallelism, up to 176 fps for VGA
images with 128 disparity levels and 4 SGM paths. This architecture will be studied
in more detail in Sect. 3.7 .

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3.3 Other Architectures

The use of programmable architectures besides GPUs has also been investigated
in some depth. Muhlmann et al. [ 66 ] investigated memory layout schemes for the
disparity space and implementations schemes including MMX optimizations for
SAD-based matching without cost aggregation (w/o CA).
A number of publications specifically target programmable embedded solutions:
An SSD with multiple window selection has been implemented on the ClearSpeed
CSX700 architecture (250 MHz, 9 W) which provides massively parallel SIMD in
multiple parallel processing elements [ 41 ] . The same algorithm has been imple-
mented [ 79 ] on the Tilera TILEPro64, which is a MIMD architecture with 64 integer
processing cores organized in a two dimensional mesh network running at MHz.