Digital Signal Processing Reference
In-Depth Information
Fig. 4
The conceptual view of RVC
B standard. A
Type-1
decoder is constructed using the FUs within the MPEG
Video Tool Library (VTL) only. Hence, this type of decoder conforms to both
the MPEG-B and MPEG-C standards. A
Type-2
decoder is constructed using
FUs from the MPEG VTL as well as one or more proprietary libraries (VTL
1-n). This type of decoder conforms to the MPEG-B standard only. Finally, a
Type-3
decoder is constructed using one or more proprietary VTL (VTL 1-n),
without using the MPEG VTL. This type of decoder also conforms to the MPEG-
B standard only. An RVC decoder (i.e. conformant to MPEG-B) is composed of
coding tools described in VTLs according to the decoder description. The MPEG
VTL is described by MPEG-C. Traditional programming paradigms (monolithic
code) are not appropriate for supporting such types of modular framework. A new
dataflow-based programming model is thus specified and introduced by MPEG RVC
as specification formalism.
The MPEG VTL is normatively specified using RVC-C
AL
. An appropriate level
of granularity for the components of the standard library is important, to enable
an effective possibility of reconfigurations, for codecs, and an efficient reuse of
components in codecs implementations. If the library is composed of too coarse
modules, such modules will be too large/coarse to allow their usage in different
and interesting codec configurations, whereas, if the granularity level of the library
component is too fine, the number of modules in the library will result to be too large
for an efficient and practical reconfiguration process at the codec implementation
side, and may obscure the desired high-level description and modeling features of
the RVC codec specifications. Most of the efforts behind the standardization of the
MPEG VTL were devoted to study the best granularity trade-off level of the VTL
components. However, it must be noticed that the choice of the best trade-off in
terms of high-level description and module re-usability, does not really affect the
potential parallelism of the algorithm that can be exploited in multi-core and FPGA
implementations.
