Signal Processing for Cryptography and Security Applications - Signal Processing Systems - page 228

Fig. 3 Hardware/Software
co-design for ECC

2.3.2 Interface

The interface between the co-processor and CPU is of vital importance, as the
HW/SW partitioning has a large impact on the performance and flexibility. Take
ECC as an example, one can immediately see the following three choices, as shown
in Fig. 3 .
When choosing P L as the partitioning point, the co-processor performs the
modular arithmetic while the CPU generates instruction sequences for point ad-
dition/doubling and all functions above. This choice is offers a very good flexibility.
On the other side, the CPU has to frequently transfer data and instructions to the
co-processor, which may become a bottleneck. If we choose P H as the partitioning
point, then the CPU only needs to send the data at the very beginning of a scalar
multiplication, and substantially reduces the communication overhead. However, it
is difficult to update the scalar multiplication algorithm since it is now implemented
in hardware.
Being able to update the functionality of an cryptographic implementation is
very important as standards may change or the old algorithm is no longer safe due
to the discovery of new attacks. For example, when new side-channel attacks are
founded, corresponding countermeasures need to be added. Thus, the co-processor
should have a certain degree of programmability. One method to achieve low
communication overhead and high flexibility is to introduce control hierarchy.
Instead of fixed state machine (FSM), a programmable micro-controller can be used
in the co-processor.

2.3.3 Low Power Architecture

When using cryptography in constrained devices, i.e. passive RFID tags and
wireless sensor nodes, power consumption becomes a big challenge. Several low
power architectures [ 36 , 49 ] for ECC have been proposed. Traditional techniques
such as reducing the hardware size, lowering the clock frequency and using clock-
gating are helpful. For ECC implementations, registers account for more than 60%
of the area and most of the dynamic power. Thus, reducing the size of register file
and register flipping can significantly reduce the power consumption.