Digital Signal Processing Reference
In-Depth Information
actual occurrences of jets should typically be sparse. When there are a small number
of sparsely distributed jets, the sorting can be accomplished in a small number
of steps. Some proposed solutions to the jet sorting problem are to perform a
hierarchal sort, in which jets are first sorted and isolated over small regions, then
sorted globally. Although this method reduces worst-case complexity by limiting
the maximum number of iterations due to the smaller area, it is not guaranteed to
produce a fully correct solution—the algorithm may end up deleting some jets that
should not have been deleted. Another option is to simply assume that jets will
always be sparsely distributed and set a hard limit on the number of iterations of
jet trimming. This approach avoids accidental jet deletions, but potentially produces
jets with incorrect energy data if many adjacent jets occur.
6
Conclusion
High-energy physics (HEP) applications present a unique range of challenges to
DSP system designers, particularly in the form of triggering systems that process
the colossal amounts of data produced by large sensor arrays and determine which
data to keep and which data to discard. From a technical standpoint, triggering
systems require massive bandwidth, low latency, and large-scale duplication and
interconnection. In the Level-1 Trigger system of the CMS experiment at the
Large Hadron Collider, the world's most advanced particle accelerator, this amounts
to a bandwidth of hundreds of gigabytes per second, a processing latency of
less than one microsecond, and thousands of interconnected FPGAs and ASICs.
From a design methodology standpoint, these applications require the adoption of
special techniques and tools to manage cost and complexity, given the particularly
large scope and long timeline of HEP development projects. Some of these
include (1) techniques for allowing rapid, inexpensive modification and upgrade
of algorithms, (2) strategies for dealing with long design windows and evolving
platforms, (3) technologies to narrow the gap between physicists and engineers
and software and hardware infrastructure, (4) practices to allow for efficient,
homogenous testing of new algorithms and their hardware implementations, and
(5) tools to ease the process of performing collaborative design work with multi-
national, interdisciplinary design teams.
DSP system design for HEP applications is an on-going research area. Some
of the current research on the SLHC upgrade project has focused on exploiting
FPGA features to provide flexible, efficient, parallel triggering architectures and
creating new algorithms and hardware designs to accommodate an accelerator
luminosity increase of an order of magnitude. Other research focuses on improving
the development process of HEP applications through dataflow descriptions and
dataflow-based tools to provide a viable intermediary between hardware and
software implementations. Furthermore, this work aims to create an infrastructure to
promote homogenous, language-independent functional testing and verification of
