Digital Signal Processing Reference
In-Depth Information
These languages may be an attractive option to physicists, as they are a convenient
means of clearly expressing mathematical algorithms. If physics algorithms are de-
veloped using functional languages, it may be possible to quickly and automatically
convert the algorithms into dataflow descriptions, calculate the optimal number of
each of the hardware modules needed to implement the algorithm, and convert the
dataflow-based designs into efficient HDL implementations that can be synthesized
and implemented in hardware.
The idea of a fully automated process to translate physics algorithms into
high-quality hardware designs is not yet feasible. Some algorithms are inherently
sequential, or are not easily translated to functional languages and dataflow descrip-
tions. Current translation tools do not yet achieve the level of quality and efficiency
required to meet the strict constraints imposed by HEP systems. However, as these
tools mature, this design flow may become more and more attractive; if not for the
final hardware design, then potentially at least for intermediate design exploration.
Reducing the need for expert hardware designers could go a long way towards
eliminating some of the firmware-design bottlenecks in the process of developing
new hardware-based physics algorithms.
4.5
Verification and Testing
HEP applications have many architecturally challenging characteristics. As an
engineer, it is tempting to focus most of the effort on the design of the hardware and
to devote less effort on testing those designs. However, for the large-scale, complex
systems used in HEP, the time it takes to test a design and verify that it properly
implements the original physics algorithms can be at least as time-consuming as the
design phase. An effective testing methodology is a crucial step in guaranteeing the
quality of the system design.
Some of the most significant challenges in functional verification of HEP
system hardware derive from the fact that separate frameworks are developed to
test the original software-based algorithmic description and the hardware-based
implementation of those algorithms. If the physicists designing software and the
engineers designing the hardware each develop their tests independently, there is
a risk that differences in the test suites may result in differences in the tested
hardware. For example, the tests may not have equivalent coverage, the corner
cases in software and those for hardware may differ, or one implementation may
make assumptions that do not hold for the other. A better approach is to attempt to
develop a single testing framework that can be used to test the software and hardware
implementations side-by-side, using identically formatted test sets. Although this
may seem like a simple concept, it is complicated by the fact that the software and
hardware implementations use different languages (C/C++ versus Verilog/VHDL)
and different simulators (sequential-step versus parallel/event-driven simulators).
One approach to take may be to move towards a more unified design flow by
incorporating the restriction of design languages and CAD tools as part of the
