High-Energy Physics - Signal Processing Systems - page 153

The original Level-1 Trigger uses high-performance ASICs to perform functions
such as generating energy sums from the calorimeter-based sensors and sorting the
energy values of the isolated particles. Other functions, such as jet reconstruction
(described further in Sect. 5.2 ) , may require frequent changes to adapt to the
performance of the accelerator.
This section presents three approaches to minimize the impact of algorithmic
changes on latency and resource use; resource reservation, worst-case analysis, and
fixed-resource and fixed-latency structures. A designer may use one or more of
these approaches to accommodate future changes to FPGA-based modules without
creating system-wide disruptions.
Resource Reservation is a fairly passive approach to handling variable latency
and resource usage. This technique simply sets aside a portion of the device
resources and targets a lower latency limit than the actual limit during the initial
design process. The purpose is to provide room for new features or algorithmic
changes within the reserved resource and latency bounds. If end-to-end latency
is a concern, modules can be designed to be capable of running at a higher-than-
expected operating frequency and even to contain “empty stages”—pipeline stages
that do not perform any computations and are reserved for later use. Resource
reservation has several advantages. First, as the percentage of committed resourced
on an FPGA increases, the likelihood that the addition of new logic will negatively
affect the latency of the existing logic also increases. More logic means more routing
congestion within the FPGA. Signals that used to be routed efficiently may now use
a longer path to reach their destination, increasing the path delay.
Typically, FPGA designers may aim for around 80 % utilization. In HEP systems,
the target utilization may be much lower due to the expected algorithmic changes
and demanding performance specifications. For example, the CMS Level-1 Trigger
upgrade plans currently mandate no more than 50 % device utilization. As a final
point, resource reservation does provide some additional degree of flexibility to
the design. Whereas the unused resources are originally intended to accommodate
necessary updates to the triggering algorithms, it is possible that some of these
resources could instead be used to add new features that were not even envisioned
in the original design, or to fix bugs that were not detected until system assembly.
The resource reservation approach, however, also clearly has negative aspects.
Since the Level-1 Trigger is a massively parallel system, leaving large portions of
device resources unused results in an increase in the total number of devices required
to implement the system. In addition to the increased device cost, this also means
more interconnection between devices and greater complexity in the Trigger's
architecture—aggravating the complexity problem that plagued the original Trigger
design. Second, there is no easy way to determine exactly what percentage of
resources should be reserved. Reserving too much adds to the cost and complexity
of the system, and reserving too little may cause problems when trying to modify
the algorithms. Without reliable predictions of the future resource needs, resource
reservation frequently is inefficiently skewed towards being either too conservative
or too aggressive.