High-Energy Physics - Signal Processing Systems - page 142

are composed of software running on general-purpose hardware. As time has passed
and hardware has become faster, new technologies have been integrated into the
hardware levels of more recent system designs. For decades, early triggers relied pri-
marily on fixed-function Application-Specific Integrated Circuits (ASICs), discrete
memories, and occasionally custom DSP processors [ 4 , 32 , 36 , 57 ] . Around the mid-
1990s, triggers began incorporating programmable logic into their triggers. Today,
ASICs still play an important role in the most performance-critical functions, but
more-flexible Programmable Logic Devices (PLDs), such as Field-Programmable
Gate Arrays (FPGAs) have become pervasive in trigger logic [ 2 , 13 , 25 , 29 , 54 ] .

2.3 The Super Large Hadron Collider Upgrade

To understand many of the motivations behind design decisions in HEP systems,
it is important to evaluate them in the context of the projects' massive size and
cost. While it is difficult to get an exact number, publicly released figures put the
direct cost of the design and construction of the Large Hadron Collider and its
experimental detectors at more than $4.3 billion as of 2010. The time from project
approval to project completion spanned over 10 years, despite the reuse of facilities
from LHC's predecessor, the Large Electron-Positron Collider. After completion,
work immediately began on the design of upgrades to the systems parameters
which may themselves take another decade. These high costs and long design times
provide a firm motivation to design the LHC to be as flexible as possible for future
needs to ensure that the useful life of the experiment can be extended, even after the
initial experiments have run their course.
The cost and time of constructing a new accelerator, coupled with funding cuts
to many scientific institutions in a difficult economic climate, have caused scientific
institutions to seek to adopt systems that can be upgraded and kept in use as long as
possible. For example, Fermilab's Tevatron, the highest-energy particle accelerator
prior to the LHC, stayed in operation for over 20 years and had several major
upgrades to extend its lifetime. To this end, the Level-1 Trigger hardware of the
LHC's CMS system is designed to strike a balance between the high-performance of
fully dedicated custom hardware and the flexibility needed to ensure that the systems
can adapt to changes in experimental parameters and research goals. Triggering
decision thresholds are fully programmable. Particle identification algorithms are
currently implemented in RAM-based look-up tables to allow adjustment or even
full replacement of the algorithms. For most of the history of trigger design, RAM-
based look-up tables were the primary means for incorporating reprogrammability
in triggering algorithms, however the potential for using them was limited due to
their high relative costs. Modern systems, like the CMS Level-1 Trigger, increase
flexibility further by replacing many fixed-function ASICs with reprogrammable
FPGAs [ 22 ] . The adoption of FPGA-based platforms is a broad trend in the
development of HEP systems and one of the key characteristics in the design of
modern systems [ 33 , 34 , 41 ] . The specific impacts of the use of FPGAs in HEP