Mapping Decidable Signal Processing Graphs into FPGA Implementations - Signal Processing Systems - page 1370

Whilst parameters such as input/output and coefficient wordlength can be easily
identified as a parameter, the implementation of the level of pipelining is much
more difficult to achieve but is important, as typically this is a key parameter in
determining the throughput rate. Therefore a sound approach is to allow a level
of pipelining to be set by the user. From a SFG perspective, this requires the
determination of the delay to be computed in terms of for each edge of the SFG,

as retiming usually results in a delay in every SFG edge following a processor and
possibly, in edges between delays. In this way, level of pipelining can be introduced
as a IP core parameter to the design, thereby giving the designer the control to adjust
the speed of the design.

α

5 Conclusions

The chapter has shown how decidable signal processing graphs are mapped into
FPGA hardware by adjusting the pipelining period and subsequently exploring
folding and unfolding. The availability of hierarchical levels of memory but specif-
ically flip-flops and distributed RAM, makes pipelining an attractive optimization
to explore in FPGA implementations, particularly with programmable interconnect
having such an impact on the critical path. The chapter has shown this for a number
of applications including a simple FIR filter and a more complex adaptive LMS
filter. In most cases, real synthesis figures from Xilinx Virtex ® -5 FPGAs have been
used to back up the theoretical analysis.
As much of the material in this topic illustrates, implementation of pipelining
within such structures increasingly only represents a component in the design of
complex DSP systems; a key feature therefore, is the efficient incorporation of
cores created for these system components in a higher level design flow which is
considered in Sect. 5.1 . Whilst the approaches in the chapter have been explored for
mostly optimization of speed against area, the implications for power are given in
Sect. 5.2 .

5.1 Incorporation of FPGA Cores into Data Flow

Based Systems

One of the knock-on effects of applying pipelining for system level DSP imple-
mentation, is the change in latency in the DSP component. For example, in the
FIR filter of Fig. 7 a , there is no delay in generating the output; however for the
transposed pipelined version (Fig. 7 d ), the impact of retiming has been to improve
the throughput rate but also to increase the latency to N delays. This latency needs
to be reflected at a higher system level. In many cases, this will have no impact as
the FIR filter most probably will be used in the creation of a more complex system