Digital Signal Processing Reference
In-Depth Information
the reasons that a TF-LMS filter has been chosen is that the delay is increased to
allow pipelining to be applied; however this compromises performance and must
be judged carefully. Thus, a key aspect of the design process is to determine the
minimum value of
m
needed to create the pipelining.
There are in effect, 16 delay loops in the circuit. Eight of the loops are trivial
and refer to the adders
A
11
,
A
81
that have one processing unit and one delay,
thus giving a pipelining period of 1. The other eight loops are given below and the
pipelining period is calculated as before. For loop 1, the path is given by
y
n
→
A
21
,...,
mD
→
A
82
which is equivalent to 5D if pipelining is to
be applied at the processor level. Given the programmable delay is
m
A
1
→
M
81
→
A
81
→
M
82
→
1, then this
gives a pipelining period
m
of 4D. By considering all of the seven other loops (only
some of which are shown), it is seen that this represents the worse case delay.
Loop 1:
y
n
→
+
mD
→
A
1
→
M
81
→
A
81
→
M
82
→
A
81
5
m
=
⇒
=
α
m
1
4
1
+
1
Loop 2:
y
n
→
mD
→
A
1
→
M
71
→
A
71
→
M
72
→
A
71
→
A
81
6
m
α
2
=
⇒
m
2
=
3
+
3
Loop 3:
y
n
→
mD
→
A
1
→
M
61
→
A
61
→
M
62
→
A
61
→
A
71
→
A
81
7
m
α
3
=
⇒
m
3
=
2
+
5
.
Loop 8:
y
n
→
mD
→
A
1
→
M
11
→
A
11
→
M
12
→
A
11
→
A
21
→
A
31
→
A
41
→
A
51
→
A
61
→
A
71
→
A
81
12
m
=
⇒
=
−
α
m
8
3
8
+
15
m
=
max all m
c
)=
4
D
The delay of 4D is then applied to the
mD
delay block and retiming is performed
repeated throughout the structure in the same way to give the final retimed circuit
delay at the output of
A
1
which symbolizes that it can be pipelined. A second cut
is applied around multiplier
M
81
and a delay transferred from the output. Due to
