Mapping Decidable Signal Processing Graphs into FPGA Implementations - Signal Processing Systems - page 1358

2.4 FPGA Design Strategy

The availability of dedicated multipliers, adders, multiply-accumulate blocks and
distributed memory either in the form of distributed RAM blocks or registers,
represents an ideal platform for implementing DSP systems. A number of points
emerge from the process of implementing DSP systems on FPGA.

￿ The availability of dedicated multipliers, adders and memory elements suggest a

direct mapping from the processing graphs to FPGAs where each function can
be implemented by a separate processing element thereby allowing high levels
of parallelism. Historically, a lot of effort had been dedicated to implementing
multiplicative functionality using the LUT-based programming element (Fig. 2 )
[ 8 , 15 , 16 ] but this has now been superseded by the recent developments in FPGA
architectures, namely the DSP blocks.

￿ The plethora of small, distributed memories suggest a highly pipelined approach

is applicable in FPGA. Pipelining not only has the benefits of improving the
throughput rate of many systems but can also act to reduce dynamic power
consumption [ 17 , 18 ] as it acts to reduce average net length and switching activity.

￿ Given that typical FPGA implementations can be clocked at between 200 and

500 MHz depending on application requirements, a key aspect is to apply hard-
ware sharing through folding to allow better utilization of the FPGA hardware.
This acts to reduce the computational hardware but acts to increase memory
requirements (to allow storage of current state for the many functions being
implemented). Efficient implementation using the available memory resource is
therefore a requirement.

3 Circuit Architecture Derivation

The availability of processing elements and distributed memory on FPGA provides
a clear focus to investigate mapping of DSP functions into highly pipelined, parallel
circuit architectures. This is demonstrated using the simple examples of FIR and
lattice filters which highlight non-recursive and recursive computations.

3.1 Basic Mapping of DSP Functionality to FPGA

As highlighted in chapter [ 12 ] , DSP systems can be represented using a SFG. This is
illustrated for the FIR filter description given in Fig. 5 a and represented by Eq. ( 1 ) .
The directed edge ( j , k ) denotes a linear transform usually given as multiplications ,
additions or delay elements, from the signal at node j to the signal at node k .The
data flow graph (DFG) representation is shown in Fig. 5 b and it shown here, as it is a