Mapping Decidable Signal Processing Graphs into FPGA Implementations - Signal Processing Systems - page 1355

(ALM) in Fig. 2 a and in the Xilinx Virtex ® -5 configurable logic block (CLB) in
Fig. 2 b . These structures are similar to those used in the latest Virtex-7 and Stratix
V FPGA families. The adder configuration in FPGAs is typically based on a ripple
carry adder structure as this can be easily scaled in terms of input/output wordlength
even though it is conventionally the slowest of the adder structures [ 10 ] . In the case
of the ALM, the adders can perform two 2-bit addition or a single ternary addition
and with the Xilinx Virtex ® , it is possible to perform a fast addition using the fast
carry logic circuitry. This gives a range of speeds from 1 ns for an 8-bit addition to
2.5 ns for a 64-bit addition.

2.2 FPGA DSP Functionality

In addition to the programmable adder structures, both FPGA families have
developed dedicated on-board DSP hardware as shown in Fig. 3 . A simplified
version of the Xilinx DSP48 hardware block (Fig. 3 a ) comprises multiplicative and
accumulation hardware which can be configured to implement one tap of an FIR fil-
ter. In addition, the programmable connectivity provided by the multiplexers (some
of which are not shown), allows a variety of modes of operation including single
stage multiplication, single stage addition, multiply accumulation and increased
arithmetic computations (achieved by chaining DSP blocks together using the
connectivity shown at the bottom of the figure). A pattern detector is also provided
on the output which gives support for a number of numerical features including
convergent rounding, overflow/underflow, block floating-point, and accumulator
terminal count (counter auto reset) with pattern detector outputs.
The Altera Stratix ® equivalent circuit is shown in Fig. 3 b . Altera have opted
for a more complex structure with four multipliers and adders/accumulators per
stage. It has been clearly developed to support a number of specific DSP functions
such as a 4-tap FIR filter, an FFT butterfly and a complex multiplication namely
( a

jd ). A number of wordlengths are supported as indicated in Table 1 .
As with the Xilinx DSP hardware, functionality is also provided to support a number
of modes of operation including looping back from the output register (useful for
recursion), connectivity of DSP block from above (as DSP blocks are connected in
columns) and dedicated rounding, underflow and overflow circuitry.

+ ib )x( c +

2.3 FPGA Memory Organization

A key aspect in FPGA is memory distribution which is important for DSP applica-
tions as pipelining is commonly used to speed up computations. The availability of
registers in each ALM and CLB as shown in Fig. 2 , allows for direct implementation