Optimization of Number Representations - Signal Processing Systems - page 1305

and delays are modeled to consume the hardware resources in proportion to their
word-lengths. The number of gates for a multiplier is dependent on the product of
two input word-lengths. Note that the hardware cost model is affected not only by
the process technology but also by the implementation architecture. When a signal
processing algorithm is implemented in a time-domain multiplexed mode, the per-
bit cost of arithmetic blocks that are shared can be lowered. Since the hardware cost
model is stored at an external file, a designer can assign an appropriate value to
each component according to the implementation architecture and the ASIC library.
In this example, the hardware cost model using VLSI Technologies' cell library is
used, and the hardware cost of 200 and 202 is assumed for each bit of ADC and
DAC, respectively. According to these models, the hardware cost increase for each
bit is 200 for group “ADC,” 227 for group “filter,” and 202 for group “DAC.”
In the exhaustive search algorithm, the word-length vector that requires the least
cost is selected in a priority for the fixed-point performance measurement starting
from the minimum word-length vector. For example, the word-length for group
“ADC” will be increased first as shown in Table 6 . If the test is failed, the word-
length for group “DAC” will be increased instead of group “ADC.” The search
sequence using the exhaustive algorithm is shown in Table 6 . The minimum cost
word-length vector determined is (12, 17, 11), and the hardware cost required is
8481. Although the result is the minimum cost solution, this method demands many
fixed-point performance measurements. The search procedure is a combinatorial
algorithm as a function of the number of groups and is practical only when the
number of groups is small, usually less than 6.
In the first heuristic search algorithm, all the word-lengths are increased by
one, e.g. the word-length vector is increased to (12, 17, 12) from the minimum
word-length vector (11, 16, 11), and the fixed-point performance is measured. If
the result is not satisfactory, the above procedure is repeated. This step requires
typically one to two simulations. After then, the word-length for a group whose
cost saving is the greatest is decreased. If it does not satisfy the performance, the
word-length is restored. This procedure is conducted for all the group, and, as a
result, requires N simulations. The maximum number of simulations required for
the heuristic search based word-length optimization, including the minimum word-
length determination, is only linearly proportional to the number of groups, N .The
word-length vector determined for the first order digital filter shown in Fig. 7 is
(12, 17, 11), which is the same as the minimum cost word-length. According to the
experiments using eight examples, the additional hardware cost is usually less than
5% of that required for the exhaustive search algorithm.
In the second heuristic search algorithm, the word-length vector that shows
the best ratio of performance increment to cost increase is selected. The word-
length of each group is increased by one bit, and the fixed-point performance is
measured using simulations for each case, and the best result is selected for the next
iteration until the desired fixed-point performance is satisfied. Since the fixed-point
performance increment is used in this method, this heuristic can be applied when
the fixed-point performance can be quantified such as SQNR. When the fixed-point