Optimization of Number Representations - Signal Processing Systems - page 1299

Fig. 15 An additive noise

model

can result in a serious problem when an accumulation circuit that has a very high
DC gain is followed. Thus, as the FWL is decreased by 1 bit, the output noise power
becomes quadrupled, and the SQNR is decreased by 6 dB. At the same way, the
increase of the FWL by 1 bit increases the SQNR by 6 dB. For more complex
systems containing multiple quantization noise sources, the additive quantization
noise model can also be built in a similar way, and the output noise is the sum of
all the quantization noise sources [ 12 ] . Therefore, the increase of all the fractional
word-lengths by 1 bit also raises the output SQNR by 6 dB in this case, too. The
SQNR as the fixed-point performance measure can also be used for waveform
coders, such as the adaptive delta modulators(ADMs) or CELP vocoders; however
the increase of all the fractional word-lengths by 1 bit does not reduce the output
noise power by 6 dB because these systems are not linear with respect to the
quantization noise sources. For the case of an adaptive filter, word-length reduction
causes slow convergence and higher steady state noise power. Thus, the fixed-point
performance for optimizing an adaptive filter can be modeled as the noise power
after some time-off period [ 22 ] .

5.2 Fixed-Point Simulation Using C ++ gFix Library

Although several analytical methods for evaluating the fixed-point performance of
a digital signal processing algorithm have been developed by using the statistical
model of quantization noise, they are not easily applicable to practical systems
containing non-linear and time-varying blocks[ 26 , 27 ] . The analysis is more com-
plicated when a specific kind of input signal, such as speech, is required for the
evaluation. In order to relieve these problems, simulation tools can be used for
evaluating the fixed-point characteristics of a digital signal processing algorithm.
There are a few commercially available fixed-point simulation tools for signal
processing. The SPD (Signal Processing Designer) of CoWare and the Simulink
of MathWorks provide fixed-point simulation libraries [ 1 , 4 ] . Mixed simulation of
floating-point and fixed-point blocks is allowed with these libraries. The fixed-point
block can be a simple adder or a quite complex one, such as FFT or digital filtering.
In order to assign a fixed-point format for each block, it is just needed to open
a block by mouse clicking and edit the fixed-point attributes for the block, such
as the word-length, integer or fractional word-length, overflow or saturation mode,
rounding or quantization mode, and so on.