Optimization of Number Representations - Signal Processing Systems - page 1297

78.5 dB for 'C50, 'C60 and Motorola 56000, respectively. Note that 'C50 uses a
16-bit word-length for internal memory, while 'C60 supports a native 32-bit word-
length, although both machines have only 16-bit multipliers. In 'C60, the upper
16 bits of the 32-bit data are multiplied to produce a 32-bit result. Thus, the 'C50
based implementation generates more quantization noise due to the truncation of
the lower 16 bits of the 32-bit multiplied result. Motorola 56000 uses a 24-bit data
type for both addition and multiplication. The upper 24 bits of the multiplier output
are used for the multiplication results. When the IWL's are increased for the shift
reduction, the fixed-point performance is slightly degraded in the 'C60 examples
because the FWL's are decreased, but the 'C50 example results do not agree with
our expectation. It is because the quantization noises due to the scale down shifts
are eliminated. In this example, the input is scaled instead of the internal signals to
reduce the scaling shifts, and it results in less quantization noise at the output signal.
Since the results of optimization as a function of the IWL increase are not simple,
we need to try a few different upper bounds to find the best one.

5 Word-Length Optimization

VLSI implementation of digital signal processing algorithms requires fixed-point
arithmetic for the sake of circuit area minimization, speed, and low-power consump-
tion. Word-length optimization is also used for 16-bit programmable DSP and SIMD
processor based implementations because some SIMD arithmetic instructions for
embedded processors employ shortened word-length, 8-bit or 16-bit, data for
increasing the data-level parallelism. In the word-length optimization, it is necessary
to reduce the quantization effects to an acceptable level without increasing the
hardware cost too much. If the number of bits assigned is too small, quantization
noise will degrade the system performance too much; on the other hand, if the
number of bits is too large, the hardware cost will become too high. Word-length
optimization for linear time-invariant systems may be conducted by analytical
methods [ 9 ] . However, the simulation based approach is preferred because these
methods allow not only linear but also non-linear and time-varying blocks [ 23 ] .
In this sub-section, the finite word-length effects will be described, a C

class
library based fixed-point simulation tool will be presented, and the simulation based
word-length optimization method will be explained.

++

5.1 Finite Word-Length Effects

Fixed-point arithmetic introduces quantization noise, and by which the final system
performance is inevitably degraded in most cases. Thus, the needed performance
of a system with fixed-point arithmetic should be defined first for word-length
optimization. Finite word-length effects for implementing a digital filter can be