Digital Signal Processing Reference
In-Depth Information
a
b
A
S
a
3
a
2
a
1
a
0
s
3
s
2
s
1
s
0
b
3
b
2
b
1
b
0
X
D
D
B
D
4
l
+0
4
l
+1,2,3
4
l
+0
4 +1,2,3
l
0
Z
c
d
a
2
a
3
b
2
b
3
A
0
A
1
S
0
S
1
a
0
a
1
b
0
b
1
X
0
X
1
B
0
D
0
B
1
D
1
l
2 +0
2
l
+
0
0
carry
out
D
2
l
+0
Z
1
Z
0
2
l
+1
2
l
+1
D
s
2
s
3
s
0
s
1
Fig. 13
4. (
b
) The DFG corresponding to the
bit-serial adder.
(c)
The DFG resulting from unfolding the DFG using unfolding factor of
J
(
a
) Bit-serial addition
s
=
a
+
b
for wordlength
W
=
=
2.
(d)
The digit-serial adder designed by unfolding the bit-serial adder using
J
=
2
For more details on how to unfold the DFG when the unfolding factor
J
is not
4.1.3
Infinite Unfolding of DFG
Any DFG can be unfolded by a factor of
. This infinitely unfolded DFG explicitly
represents all intra-iteration and inter-iteration constraints. These DFGs correspond
to dependence graphs (DGs) of traditional terminating programs. The DG or the
∞
4.2
Folding
The folding transformation is used to systematically determine the control circuits
in DSP architectures where multiple algorithm operations such as additions are
time-multiplexed to a single functional unit such as pipelined adder. By executing
multiple algorithm operations on a single functional unit, the number of functional
units in the implementation is reduced, resulting in an integrated circuit with low
