Digital Signal Processing Reference
In-Depth Information
a
b
c
d
Fig. 11
(
a
) The original DSP program. (
b
) The DFG for (
a
).
(c)
The 3-unfolded DFG.
(d)
The
3-parallel DSP program
Word-Level Parallel Processing
In general, unfolding a word-serial architecture by
J
creates a word-parallel
architecture that processes
J
words per clock cycle. As an example, consider the
DSP program
y
architecture that can process more than 1 word per clock cycle, the first step is to
(
n
)=
ax
(
n
)+
bx
(
n
−
4
)+
cx
(
n
−
6
)
