Signal Flow Graphs and Data Flow Graphs - Signal Processing Systems - page 1264

Fig. 9 ( a ) A datapath. ( b )
The 2-level pipelined
structure of ( a )

a

a(n) b(n)

x(n)

y(n)

b

a(n) b(n−1)

x(n)

D y(n−1)

Pipelining transformation leads to a reduction in the effective critical path by
introducing pipelining registers along the datapath, which can be exploited to either
increase the clock speed or sample speed or to reduce power consumption at
same speed. Consider the simple structure in Fig. 9 a , where the computation time of
the critical path is 2 T A . Figure 9 b shows the 2-level pipelined structure, where one
register is placed between two adders and hence the critical path is reduced by half.
Obviously, in an M -level pipelined system the number of delay elements in any
path from input to output is greater than that in the same path in the original

sequential circuit. While pipelining offers the benefit of critical path reduction, its
two drawbacks lie in the increase in the number of registers and the system latency,
which is the time difference in the availability of the first output data in the pipelined
system and the sequential system.

( M − 1 )

4 Applications to Hardware Design

In this section, two DFG-based high-level transformations applicable to practical
hardware design such as field programmable gate array (FPGA) or application
specific integrated circuit (ASIC) implementations are introduced, one is the
unfolding transformation, and the other is the folding transformation. Examples will
be given to demonstrate their usage in hardware design. For more details on how to
map the decidable signal processing graphs to FPGA implementation, the reader is
referred to [ 1 ] .

4.1 Unfolding

Unfolding is a transformation technique that can be applied to a DSP program to
create a new program describing more than one iteration of the original program.
More specifically, unfolding a DSP program by the unfolding factor J creates a new