Software Compilation Techniques for MPSoCs - Signal Processing Systems - page 1213

Fig. 9 a , is not exploited. Besides, depending on the architecture, this partition may
require the array A to be sent through the interconnect, which could be too costly.
ThescheduleinFig. 10 b uses the information gathered by the dependence analysis
in Fig. 9 and exploits fully the TLP and the DLP available in the application. This
behavior can be obtained by unrolling the loop at the granularity shown in Fig. 6 b .
In this example, task T1 dominates the execution of the complete application
and therefore processors RISC2-RISC5 feature a low utilization. To improve the
utilization, two tasks T3 are merged into T3' asshowninFig. 10 c . Finally, if the
DSPisusedtoexecutetask T2 , a similar execution time of the application can be
obtained by using only two processing elements as illustrated in Fig. 10 d . Note that
the last partition corresponds to the task-level granularity in Fig. 6 c .
The previous example is of course too simplistic and serves only as an illustration
of the importance of timing information. In this example no interconnect nor
access to share resources such as peripherals or memory were modeled. For real
applications it is much more difficult to characterize the timing behavior and the
resource usage. It might be impractical to characterize the timing behavior of a code
block with a simple average value. For some applications, a discrete set of values
for different scenarios might be used [ 29 , 58 ] . For other applications a more detailed
statistical description in form of a probability density function could be required
[ 43 ] . Access to shared resources can be modeled in a similar way to reservation
tables. Several code blocks might access the same resources in the MPSoC (e.g.
analog-to-digital converters, serial communication links, graphical display) and
these structural hazards need to be taken into account by the MPSoC compiler.

Summary

Platform models for MPSoC compilers describe similar features to those of
traditional compilers but at a higher level. Processing elements and NoCs take the
place of functional units, register files and their interconnections. On an MPSoC
compiler, the platform model is no longer restricted to be used on the back end but a
subset of it may be used by the front end and the middle end. Out of the information
needed to describe the platform, the timing behavior is the most challenging. This
timing information is needed for performing successfully mapping and scheduling,
as will be described in the next section.

2.4 Mapping and Scheduling

Mapping and scheduling in a traditional compiler is done in the back end provided a
description of the architecture. Mapping refers to the process of assigning operations
to instructions and functional units (code selection) and variables to registers