Software Compilation Techniques for MPSoCs - Signal Processing Systems - page 1196

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Fig. 1 Coarse view of uni-processor compiler phases

actual code generation and is divided into phases as well. Typical back end phases
include code selection , register allocation and instruction scheduling . These phases
are machine dependent and therefore require a model of the target architecture.
As in the uni-processor case, MPSoC compilers are also divided into phases
in order to manage complexity. Throughout this section more details about these
phases will be given, as they help to understand the differences between uni-
processor and multi-processor compilers. The overall structure of the compiler (in
Fig. 1 ) will suffer some changes though. On the one hand, if the programming model
makes some architecture features visible to the programmer, the front end will need
information of the target platform. On the other hand, the back end should be aware
of formal properties of the programming model that may ease the code generation.

2.1 Programming Models

The main entry for any compiler is a representation of an application using a given
programming model (see Fig. 1 ) . A programming model is a bridge that provides
humans access to the resources of the underlying hardware platform. Designing
such a model is a delicate art, in which hardware details are hidden for the sake
of productivity and usually at the cost of performance. In general, the more details
remain hidden, the harder the job of the compiler is to close the performance gap.
In this sense, a given programming model may reduce the work of the compiler
but will never circumvent using one. Figure 2 shows an implementation of an FIR
filter with different programming languages representing different programming
models. The figure shows an example of the productivity-performance trade-off.
On one extreme, the Matlab implementation (Fig. 2 a ) features high simplicity
and no information of the underlying platform. The C implementation (Fig. 2 b )
provides more information, having types and the memory model visible to the
programmer. On the other extreme, the DSP-C implementation (Fig. 2 c ) has explicit
memory bank allocation (through the memory qualifiers X and Y ) and dedicated data