Compiling for VLIW DSPs - Signal Processing Systems - page 1187

11. Andrzej Bednarski and Christoph Kessler. Optimal integrated VLIW code generation with
integer linear programming. In Proc. Int. Euro-Par 2006 Conference . Springer LNCS, August
2006.
12. Mirza Beg and Peter van Beek. A constraint programming approach for instruction assignment.
In Proc. Int. Workshop on Interaction between Compilers and Computer Architectures
(INTERACT-15) , pp. 25-34, February 2011.
13. D. Bernstein, M.C. Golumbic, Y. Mansour, R.Y. Pinter, D.Q. Goldin, H. Krawczyk, and
I. Nahshon. Spill code minimization techniques for optimizing compilers. In Proc. Int. Conf.
on Progr. Lang. Design and Implem. , pages 258-263, 1989.
14. F. Bouchez, A. Darte, C. Guillon, and F. Rastello. Register allocation: what does the NP-
completeness proof of Chaitin et al. really prove? [...]. In Proc. 19th int. workshop on
languages and compilers for parallel computing, New Orleans , November 2006.
15. Thomas S. Brasier, Philip H. Sweany, Steven J. Beaty, and Steve Carr. Craig: A practical
framework for combining instruction scheduling and register assignment. In Proc. Int. Conf.
on Parallel Architectures and Compilation Techniques (PACT'95) , 1995.
16. Preston Briggs, Keith Cooper, Ken Kennedy, and Linda Torczon. Coloring heuristics for
register allocation. In Proc. Int. Conf. on Progr. Lang. Design and Implem. , pages 275-284,
1989.
17. Preston Briggs, Keith Cooper, and Linda Torczon. Rematerialization. In Proc. Int. Conf. on
Progr. Lang. Design and Implem. , pages 311-321, 1992.
18. Philip Brisk, Ajay K. Verma, and Paolo Ienne. Optimistic chordal coloring: a coalescing
heuristic for SSA form programs. Des. Autom. Embed. Syst. , 13:115-137, 2009.
19. G.J. Chaitin, M.A. Auslander, A.K. Chandra, J. Cocke, M.E. Hopkins, and P.W. Markstein.
Register allocation via coloring. Computer Languages , 6:47-57, 1981.
20. Chia-Ming Chang, Chien-Ming Chen, and Chung-Ta King. Using integer linear programming
for instruction scheduling and register allocation in multi-issue processors. Computers Mathe-
matics and Applications , 34(9):1-14, 1997.
21. Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han
Lu, and Jenq-Kuen Lee. Enabling compiler flow for embedded VLIW DSP processors with
distributed register files. In Proc. LCTES'07 , pages 146-148. ACM, 2007.
22. Hong-Chich Chou and Chung-Ping Chung. An Optimal Instruction Scheduler for Superscalar
Processors. IEEE Trans. on Parallel and Distr. Syst. , 6(3):303-313, 1995.
23. Michael Chu, Kevin Fan, and Scott Mahlke. Region-based hierarchical operation partitioning
for multicluster processors. In Proc. Int. Conf. on Progr. Lang. Design and Implem. (PLDI'03) ,
pp. 300-311, ACM, June 2003.
24. Josep M. Codina, Jesus Sanchez, and Antonio Gonzalez. A unified modulo scheduling and
register allocation technique for clustered processors. In Proc. PACT-2001 , September 2001.
25. Edward S. Davidson, Leonard E. Shar, A. Thampy Thomas, and Janak H. Patel. Effective con-
trol for pipelined computers. In Proc. Spring COMPCON75 Digest of Papers , pages 181-184.
IEEE Computer Society, February 1975.
26. Giuseppe Desoli. Instruction assignment for clustered VLIW DSP compilers: a new approach.
Technical Report HPL-98-13, HP Laboratories Cambridge, February 1998.
27. Dietmar Ebner. SSA-based code generation techniques for embedded architectures . PhD thesis,
Technische Universitat Wien, Vienna, Austria, June 2009.
28. Erik Eckstein, Oliver Konig, and Bernhard Scholz. Code instruction selection based on SSA-
graphs. In A. Krall, editor, Proc. SCOPES-2003, Springer LNCS 2826 , pages 49-65, 2003.
29. Alexandre E. Eichenberger and Edward S. Davidson. A reduced multipipeline machine
description that preserves scheduling constraints. In Proc. Int. Conf. on Progr. Lang. Design
and Implem. (PLDI'96) , pages 12-22, New York, NY, USA, 1996. ACM Press.
30. Christine Eisenbeis and Antoine Sawaya. Optimal loop parallelization under register

constraints. In Proc. 6th Workshop on Compilers for Parallel Computers (CPC'96) ,

pages 245-259, December 1996.
31. John Ellis. Bulldog: A Compiler for VLIW Architectures. MIT Press, Cambridge, MA, 1986.