Digital Signal Processing Reference
In-Depth Information
constant loop setup cost. Also, they do not suffer from control hazards, as the
processor hardware knows well ahead of time where and whether to execute the
next backward branch.
1.6
Examples of VLIW DSP Processors
In the next section, we will consider the TI'C62x DSP processor as a case study.
Other VLIW/EPIC DSP processors include, e.g., the HP Lx/STMicroelectronics
2
Case Study: TI 'C62x DSP Processor Family
As a case study, we consider a representative of Texas Instrument's C62x™/C64x™/
C67x™ family of clustered VLIW fixed-point digital signal processors (DSPs) with
the VelociTI™ instruction set.
performance fixed-point digital signal processor (DSP) clocked at 200 MHz. It is a
clustered VLIW architecture with issue width
ω
=
8. A block diagram is given in
The 'C6201 has eight functional units, including two 16-bit multipliers for 32-
bit results (the .M-units) and six 32/40-bit arithmetic-logical units (ALUs), of which
two (the .D-units) are connected to on-chip data cache memory. The 'C62x CPUs
are load-store architectures, i.e., all operands of arithmetic and logical operations
must be constants or reside in registers, but not in memory. The data addressing
(.D) units are used to load data from (data) memory to registers and store register
contents to (data) memory. The load and store instructions exist in variants for 32-
bit, 16-bit and 8-bit data. The two .L units (logical units) mainly provide 32-bit
and 40-bit arithmetic and compare operations and 32-bit logical operations like and,
Program
cache / Program
memory
Register file A (A0−A15)
Register file B (B0−B15)
2X
1X
.L1
.S1
.M1
.D1
.D2
.M2
.S2
.L2
Data cache / Data memory
Fig. 6
The TI 'C6201 clustered VLIW DSP processor
