Digital Signal Processing Reference
In-Depth Information
Cluster 1
Cluster 2
Cluster N
Register File 1
Register File 2
Register File N
...
...
...
...
FU
...
FU
FU
...
FU
FU
...
FU
Interconnection Network
Fig. 5
Clustered VLIW processor with partitioned register set
is usually referred to as the
delay
4
The difference
(
i
1
,
i
2
)
−
o
(
i
1
,
i
2
)
of instruc-
tion
i
1
.
1.3
Clustered VLIW: Partitioned Register Sets
In VLIW architectures, possibly many instructions may execute in parallel, each
accessing several operand registers and/or producing a result value to be written
to some register. If each instruction should be able to access each register in a
homogenous register set, the demands on the number of parallel read and write
ports to the register set, i.e., on the access bandwidth to the register set, become
extraordinarily high. Register files with many ports have very high silicon area and
energy costs, and even access latency grows.
A solution is to constrain general accessibility and partition the set of functional
units and likewise the register set to form
clusters
. A cluster consists of a set of
unit can access each local register. However, the number of accesses to a remote
register is strictly limited, usually to one per clock cycle and cluster. A task for
the programmer (or compiler) is thus to plan in which cluster data should reside at
runtime and on which cluster each operation is to be performed to minimize the loss
of ILP due to the clustering constraints.
1.4
Control Hazards
The pipelined execution of instructions on modern processors, including VLIW
processors, achieves maximum throughput only in the absence of data hazards,
structural hazards, and control hazards. In VLIW processors, these hazards are
exposed to the assembler-level programmer or compiler. Data hazards and structural
hazards have been discussed above.
4
Note that in some papers and texts, the meanings of the terms
delay
and
latency
are reversed.
