Digital Signal Processing Reference
In-Depth Information
A L U
M U L T I P L I E R
A L U
M U L T I P L I E R
add:
mul:
issue
unit
read
src1
opnd
read
src2
opnd
stage
0
stage stage stage stage stage
1
write
result
bus
issue
unit
read
src1
opnd
read
src2
opnd
stage
0
stage stage stage stage stage
1
write
result
bus
0
1
2
3
0
1
2
3
Time
0
1
2
3
Time
0
1
2
3
4
5
...
t: mul ...
t+1: ...
structural
t+2: add ...
hazard
...
at t+5
Fig. 3
To p
: Example reservation tables for addition and multiplication on a pipelined processor
with an ALU and multiplier unit. Resources such as register file access ports and pipeline stages on
the functional units span the horizontal axis of the reservation tables while time flows downwards.
Time slot 0 represents the issue time.
Bottom
: Scheduling an
add
instruction two clock cycles
after a
mul
instruction would lead to conflicting subscriptions of the result resource (write back
to register file). Here, the issue of
add
would have to be delayed to, say, time
t
3. If exposed to
the programmer/compiler, a
nop
instruction could be added before the
add
to fill the issue slot at
time
t
+
2. Otherwise, the processor will handle the delay automatically by stalling the pipeline for
one cycle
+
computational kernels of typical DSP applications. For instance, Gangwar et al.
degree of 20 on average for a (clustered) VLIW architecture with 16 ALUs and
8 load-store units. Moreover, program transformations can be applied to increase
exploitable ILP; we will discuss some of these later in this chapter.
1.1
Resource Modeling
We model instruction issue and resource usage explicitly. An instruction
i
issued at
resources (such as functional units or buses) at time
t
or later.
For each instruction type, its required resource reservations relative to the issue
row
j
and column
u
indicates if the instruction uses resource
u
in clock cycle
t
j
.
If an instruction is issued at a time
t
, its reservations of resources are committed
to a
global resource usage map
or
table
. Two instructions are in conflict with each
other if their resource reservations overlap in the global resource usage map; this is
also known as a
structural hazard
.SeeFig.
3
for an example. In such a case, one of
the two instructions has to be issued at a later time to avoid duplicate reservations
of the same resource.
+
2
NOP
(no operation) instructions only occupy an issue slot but no further resources.
