Systolic Arrays - Signal Processing Systems - page 1120

Fig. 22 CORDIC systolic array [ 21 ]

Fig. 23 Processing node
architecture [ 21 ]

The PN architecture is depicted in Fig. 23 where two CORDIC processing
elements, two delay processing elements are interconnected via the communication
agent, which also handles external communications with other PNs.
Using this CORDIC reconfiguration systolic array, a minimum mean square error
detector is implemented for an OFDM (orthogonal frequency division modulation)
MIMO (multiple input, multiple output) wireless transceiver. A QR decomposition
recursive least square (QRD-RLS) triangular systolic array is implemented on a
FPGA prototype system and is shown in Fig. 24 .