Systolic Arrays - Signal Processing Systems - page 1110

Fig. 11 Photograph of iWarp

chip [ 3 ]

programmer bears the responsibility of writing a deadlock free parallel program to
run on the Warp processor array.
The performance of the Warp processor array is reported as hundreds of times
faster than running the same type of algorithm in a VAX 11/780, a popular mini-
computer at the time of Warp development.
The development of the Warp processor array is significant in that it is the
first hardware systolic array implementation. Lessons learned from this project also
motivated the development of iWarp.
The iWarp project [ 3 , 7 ] was a follow-up project of WARP and started in 1988.
The purpose of this project is to investigate issues involved in building and using
high performance computer systems with powerful communication support. The
project led to the construction of the iWarp machines, jointly developed by Carnegie
Mellon University and Intel Corporation.
As shown in Fig. 11 , the basic building block of the iWarp system is a full
custom VSLI component integrating a LIW (long instruction word) microprocessor,
a network interface and a switching node into one single chip of 1.2 1.2 cm silicon.

The iWarp cell consists of a computation agent, a communication agent, and a local
memory. The computation agent includes a 32-bit microprocessor with 96-bit wide
instruction words, an integer/logic unit, a floating-point multiplier, and a floating-
point adder. It runs at a clock speed of 20 MHz. The communication agent has four
separate full duplex physical data links capable of transferring data at 40 MB/s.

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