Digital Signal Processing Reference
In-Depth Information
of multiprocessor scheduling; If multiple tasks are running concurrently, resource
contention may lengthen the execution of the graph when a node takes shorter time
than its worst case execution time.
Since many DSP applications involve multiple tasks running concurrently, we
need to consider multi-tasking in parallel scheduling. One solution is to statically
schedule the multiple tasks up to their hyper-period that is defined as a least common
multiple of all task periods. Since the hyper-period can be huge if the task periods
are relatively prime, this approach may not be applicable. Multiprocessor scheduling
of multi-tasking applications on heterogeneous multiprocessor systems still remains
an open problem. With a given schedule, it is not yet possible to decide whether the
schedule can satisfy the real-time constraints if some nodes have varying execution
times and/or there are resource contentions during execution.
2.4
Hardware Synthesis from SDF Graph
While the target architecture is given as a constraint for software synthesis, the
target hardware structure can be synthesized in hardware synthesis from an SDF
graph. Therefore, we can achieve the
iteration bound
of an SDF graph in theory
limitation on the hardware size. Since there is a trade-off between hardware cost
and the throughput performance, however, architecture design and node scheduling
should be considered simultaneously under given design constraints.
A key issue in hardware synthesis is to preserve the SDF semantics to maintain
the correctness of the graph. In the SDF model, two samples that have the same value
should be distinguished as separate samples while the same value is not identified
as a new event in a hardware logic. So the arrival of an input sample should be
notified somehow. And if a node has more than one input port, the node should
wait until all input ports receive data samples before the node starts execution. It
means that we need some control logic to perform scheduling of the nodes. There
are two types of controllers: distributed controller and centralized controller. In the
centralized control scheme, the execution timing of each node is controlled by a
central scheduler. The execution timing can be determined at compile-time by static
scheduling of the graph. In a distributed scheme, a node is associated with a control
logic that monitors the input queues and triggers the node execution when all input
queues have input samples to fire the node.
For hardware synthesis, a node should be specified by a hardware description
language that will be synthesized by a CAD tool, or by a function block that is
mapped to a pre-defined hardware IP. If an hardware IP is used, interface between
the IP and the rest of the system should be designed carefully. Since the interface
design is a laborious and error-prone task, extensive researches are being performed
on the automatic interface synthesis.
In summary, hardware synthesis from a SDF graph involves the following
problems: architecture and datapath synthesis, controller synthesis, and interface
