C Compilers and Code Optimization for DSPs - Signal Processing Systems - page 1019

Within an optimizing compiler the coalescing of repeated instruction sequences
is typically performed on a low-level intermediate representation . 2 When applied
at a lower level, possibly after register allocation, the identification of repeated
instruction sequences should not be restricted to exact, instruction-by-instruction
matches, but allow for some abstraction of branches and registers. Two regions may
only differ in the use of labels or register names and by treating these similar regions
as matches the overall effectiveness of code compression can be increased.
References
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2 A high-level representation is used in Fig. 16 to preserve clarity and brevity of the example.