C Compilers and Code Optimization for DSPs - Signal Processing Systems - page 1012

Sequential Execution

1. Iteration 2. Iteration 3. Iteration 4. Iteration 5. Iteration

Software Pipelining

1. Iteration

2. Iteration

3. Iteration

4. Iteration

5. Iteration

Prologue Body Epilogue

Time

Fig. 12 Software pipelining

3.3.6 Software Pipelining

Software Pipelining [ 2 ] is a low-level loop optimization and VLIW scheduling
technique. It aims at exploiting parallelism at the instruction level by overlapping
consecutive iterations of a loop so that a faster execution rate is realized (see
Fig. 12 ) . Instead of executing loop iterations in sequential order software pipelining
partially overlaps loop iterations. After a number of initial iterations that are
summarized in a loop prologue a stable and repetitive scheduling pattern for the loop
body emerges. In the example instructions from three loop iterations are executed
simultaneously. Eventually, the epilogue code executes the remaining instructions
that do not belong to this repeated pattern towards the end of the loop.
Software pipelining is highly important for VLIW processors. More details can
be found in [ 21 ] .

3.4 Memory Optimizations

Memory optimizations play an important role when memory latency or bandwidth
form a bottleneck. In this section we discuss one memory optimization of particular
importance to DSPs as it deals with dual memory banks and the partitioning and
assignment of variables to these memories.