C Compilers and Code Optimization for DSPs - Signal Processing Systems - page 1004

a

b
c
d

e
f

Addressing costs: 9

b
c
d
a

f
e

Addressing costs: 4

Fig. 3 Example: addressing costs of different memory layout schemes

compiler-time. They do not incur the overhead for increment and branch instruc-
tions for each iteration, but instead a zero overhead loop is initialized once and
subsequently a fixed number of instructions is executed a specified number of times.
Constraints regarding the number of instructions in the loop body, whether or not
control flow instructions are permissible inside a zero overhead loop, the nesting
of zero overhead loops, early exits or function calls complicate code generation for
zero overhead loops because a number of checks need to be performed [ 40 , 46 ] .
A conventional loop implementation with an explicit termination test is shown
in Fig. 4 a . For each of the ten iterations a sequence of increment, comparison
and branch instructions needs to be executed. Compare this to the code fragment
in Fig. 4 b where a zero overhead loop is used and no additional instructions are
required after the initial loop setup.
While zero overhead loops are conceptually simple to exploit within a compiler,
it is the number and type of constraints that sometimes make it difficult to generate
code for zero overhead loops for all applicable loops. For example, many compiler
frameworks generate the loop control code before code for the loop body is
generated. This is problematic if the architecture places constraints on the maximum
size of the loop body of a zero overhead loop. Possible solutions include to defer
the decision on zero overhead loop code generation if the compiler framework is
flexible enough to allow this, or to rely on a conservative heuristic concerning the
ratio of intermediate operations to machine instructions.