Digital Signal Processing Reference
In-Depth Information
LM110 Op-amp
V
+
Output signal
x
o
(t)
-
Input signal
x
c
(t)
+
NTE 2377
MosFET
V
C
1
=
1
µ
F
R
1
=10
Ω
R
2
= 1200
Ω
Pulse signal
s(t)
FIGURE 4.8
Practical MosFET sample and hold circuit.
When a pulse train
s
(
t
) is high at the sample input, the FET is turned on
(during the
on
cycle) and acts as low resistance to the input signal. When
the sample pulse is absent, the MOSFET is turned off and acts as high
impedance. The desired voltage is held by capacitor
C
1
, which is isolated
from the output by the high input impedance op-amp. When the switch is
closed, the capacitor charges to
x
c
(max)
.
After the switch is opened, the capac-
itor remains charged and
x
o
(
t
) will be at the same potential as the capacitor.
The sampled voltage will be held temporarily, the time being determined
by leakage in the circuit.
a.
Connect the circuit as shown in
Figure 4.9
, and apply a 1 kHz (input
signal frequency) sinusoidal signal to the input of the S & H circuit.
Use a 10 kHz (sampling frequency) pulse signal to drive the sample
input of the S & H circuit. Observe the sampled output at the output
of the circuit on an oscilloscope.
b.
Repeat the experiment for the maximum input signal frequency
possible. Please note that the sample frequency should be accord-
ingly increased in order to obtain the required number of samples.
c.
Plot the spectra of the input and output signals of the S & H circuit
on the HP35665A Dynamic Signal Analyzer. Comment on the dif-
ferences between the two spectra.
