Digital Signal Processing Reference
In-Depth Information
followed by linear filtering with the Zero-Order Hold (ZOH) system. The
output of the ZOH system is the staircase waveform shown in
Figure 4.5b
.
The sample values are held constant during the sampling period of
T
sec-
onds.
In the design of the sample and hold circuit on Simulink, the following
three important blocks will have to be designed accurately:
•
The source signal block x
s
(t):
Assume a sinusoidal signal having a peak-
to-peak amplitude of 1 V, and a frequency of 20 Hz. Since this block's
parameters are fixed, no further design is necessary on this block.
•
The pulse train block s(t):
Two important parameters will have to be
designed for this block. The first is the pulse amplitude, and the second
is pulse period
T
sec. You can assume a rectangular pulse with 50%
duty cycle (i.e., half period on and half period off). Because this pulse
train samples the source signal, its frequency should be many times
higher than that of the source signal.
•
The Zero-Order Hold block:
One important parameter will have to be
designed for this block, which is the sampling period of the hold
circuit. The sampling period of the circuit should be sufficient to
hold the sample value over each period of the pulse train.
Practical circuit for D/A conversion:
The schematic of a practical D/A circuit is shown in Figure 4.6
a.
Select an appropriate audio signal from the Simulink DSP blockset
library as the test signal in this simulation. Plot the signal on the
scope and the FFT scope to obtain the frequency content of the signal.
This will provide information on the maximum frequency content
of the signal and the required sampling rate limits. Sample the signal
at the Nyquist rate.
b.
Design the required parameters of the A/D circuit given in Figure 4.5a
to obtain the appropriate staircase pattern as shown in Figure 4.5b.
Plot the output of the Zero-Order Hold circuit as seen on the scope
block of the Simulink program.
c.
Design a uniform quantizer to convert the sampled signal into quan-
tized signal output in numerical or binary form.
Quantize
d
signal
Quantizer
decoder
Zero-Order
Hold
h
0
(t)
Reconstruction
filter
Reconstructed
Signal
x
s
(t)
x
0
(t)
FIGURE 4.6
Schematic of digital to analog (D/A) conversion circuit.
