Digital Signal Processing Reference
In-Depth Information
EMIF
Program
On-board and
Daughter Card
Codecs
LIP Cache
M-BSPs
L2
Memory
Timers
C6711 DSP core
(CPU)
HPI
Enhanced
DMA
Controller
Interrupt
Selector
Power down logic
Data
LID Cache
Boot Configuration
PLL
FIGURE E.2
TMS320C6711 DSP chip layout. (Courtesy of Texas Instruments Inc., Dallas, TX.)
them are used for timing, and the other two are connected to the data receive
and data transmit pins on the on-board codec or daughter card. Also
included in each McBSP is a 32-bit serial port control register (SPCR). This
register is updated when the on-board codec (or daughter card) is ready to
send data to or receive data from the CPU. The status of the SPCR will only
be a concern to us when polling methods are implemented.
In the labs described in this topic, we will be exploring two possible ways
of establishing a
real-time
communication link between the CPU and the on-
board codec. The idea of real-time communication is that we want a contin-
uous stream of samples to be sent to the codec. In our case, we want samples
to be sent at rate 8 kHz (one sample every .125ms). This is controlled by the
codec, which will signal serial port 0 (SP0), every .125ms or, in the case of a
daughter card, every (1
/
24)
*
10
-3
=
0.0417 ms.
•
Polling
The first method for establishing a real-time communication link
between the CPU and the on-board codec is
polling
. When the on-
board codec is ready to receive a sample from the CPU, it sets bit
17 of the SPCR in the McBSP on the DSP chip to true. Bit 17 of the
SPCR is the CPU transmit ready (XRDY) bit, which the on-board
codec uses to let the CPU know when it can transmit data2. In a
polling application, the CPU continuously checks the status of the
SPCR and transmits a data sample as soon as bit 17 of the SPCR is
set to true. Upon transmission, the McBSP will reset bit 17 of the
SPCR to false. The polling program will then wait until the on-board
codec resets bit 17 to true before transmitting the next data sample.
In this manner, a polling algorithm will maintain a constant stream
of data flowing to the on-board codec.
On the DSP hardware, polling is implemented mostly in software.
The on-board codec will continuously set the transmit-ready bit of
the SPCR, and the McBSP on the DSP chip will always reset it.
However, it is up to the programmer to write a program that will
