Digital Signal Processing Reference
In-Depth Information
development costs and availing aftermarket feature enhancements
with mere code downloads. Consequently, when you see ASICs in
real-time signal processing applications, they are typically employed
as bus interfaces, glue logic, or functional accelerators for a program-
mable DSP-based system.
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The GPP Alternative
In contrast to ASICs that are optimized for specific functions, gen-
eral-purpose microprocessors are best suited for performing a broad
array of tasks. However, for applications in which the end product
must process answers in real time or must do so while powered by
consumer batteries, GPPs' comparatively poor real-time perfor-
mance and high power consumption all but rule them out. More
and more, these processors are being seen as the dinosaurs of the
industry — too encumbered with PC compatibility and desktop
features to adapt to the changing real-time market place, as where
world embraces tiny hand-held wireless-enabled products that
require power dissipation measured in milliwatts — not the watts
that these processors consume. Hence, DSPs are the programmable
technology of choice. That trend is bound to continue as digital
Internet appliances get smaller, faster, and more portable.
E.2
Texas Instruments DSP Product Tree
The following list gives the TI DSP product line, starting with the latest
product line.
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C6000
TMS320C6000 High Performance DSPs deliver new levels of
C-based performance and cost efficiency, with low power dissipa-
tion, for broadband networks and digitized imaging applications.
Includes code compatible C62x and C64x fixed-point DSPs; C67x
floating-point DSPs.
•
C5000
TMS320C5000 Power Efficient DSPs deliver an optimal combination
of performance, peripheral options, small packaging, and the best
power efficiency for personal and portable Internet and wireless
communications. Includes code compatible C54x and C55x fixed-
point DSPs.
•
C2000
TMS320C2000 Control Optimized DSPs deliver highest perfor-
mance, greatest code efficiency, and optimal peripheral integration
