Hardware Reference
In-Depth Information
which consists of a set of conventional registers that can be loaded from memory in
a single instruction, which actually loads them from memory serially. Then a vec-
tor addition instruction performs the pairwise addition of the elements of two such
vectors by feeding them to a pipelined adder from the two vector registers. The re-
sult from the adder is another vector, which can either be stored into a vector regis-
ter or used directly as an operand for another vector operation. The SSE (Stream-
ing SIMD Extension) instructions available on the Intel Core architecture use this
execution model to speed up highly regular computation, such as multimedia and
scientific software. In this respect, the Intel Core architecture has the ILLIAC IV
as one of its ancestors.
Multiprocessors
The processing elements in a data parallel processor are not independent
CPUs, since there is only one control unit shared among all of them. Our first par-
allel system with multiple full-blown CPUs is the
multiprocessor
, a system with
more than one CPU sharing a common memory, like a group of people in a room
sharing a common blackboard. Since each CPU can read or write any part of
memory, they must coordinate (in software) to avoid getting in each other's way.
When two or more CPUs have the ability to interact closely, as is the case with
multiprocessors, they are said to be tightly coupled.
Various implementation schemes are possible. The simplest one is to have a
single bus with multiple CPUs and one memory all plugged into it. A diagram of
such a bus-based multiprocessor is shown in Fig. 2-8(a).
Local memories
Shared
memory
Shared
memory
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
Bus
Bus
(a)
(b)
Figure 2-8.
(a) A single-bus multiprocessor. (b) A multicomputer with local
memories.
It does not take much imagination to realize that with a large number of fast
processors constantly trying to access memory over the same bus, conflicts will re-
sult. Multiprocessor designers have come up with various schemes to reduce this
