Hardware Reference
In-Depth Information
Suppose that a typical interpreted instruction took the interpreter 10 instructions,
called
microinstructions
, at 100 nsec each, and two references to main memory, at
500 nsec each. Total execution time was then 2000 nsec, only a factor-of-two
worse than the best that direct execution could achieve. Had the control store not
been available, the instruction would have taken 6000 nsec. A factor-of-six penalty
is a lot harder to swallow than a factor-of-two penalty.
During the late 70s there was experimentation with very complex instructions,
made possible by the interpreter. Designers tried to close the ''semantic gap'' be-
tween what machines could do and what high-level programming languages re-
quired. Hardly anyone thought about designing simpler machines, just as now not
a lot of research goes into designing less powerful spreadsheets, networks, Web
servers, etc. (perhaps unfortunately).
One group that bucked the trend and tried to incorporate some of Seymour
Cray's ideas in a high-performance minicomputer was led by John Cocke at IBM.
This work led to an experimental minicomputer, named the
801
. Although IBM
never marketed this machine and the results were not published until years later
(Radin, 1982), word got out and other people began investigating similar architec-
tures.
In 1980, a group at Berkeley led by David Patterson and Carlo S´quin began
designing VLSI CPU chips that did not use interpretation (Patterson, 1985, Patter-
son and S´quin, 1982). They coined the term
RISC
for this concept and named
their CPU chip the RISC I CPU, followed shortly by the RISC II. Slightly later, in
1981, across the San Francisco Bay at Stanford, John Hennessy designed and fabri-
cated a somewhat different chip he called the
MIPS
(Hennessy, 1984). These
chips evolved into commercially important products, the SPARC and the MIPS, re-
spectively.
These new processors were significantly different than commercial processors
of the day. Since they did not have to be backward compatible with existing prod-
ucts, their designers were free to choose new instruction sets that would maximize
total system performance. While the initial emphasis was on simple instructions
that could be executed quickly, it was soon realized that designing instructions that
could be
issued
(started) quickly was the key to good performance. How long an
instruction actually took mattered less than how many could be started per second.
At the time these simple processors were being first designed, the charac-
teristic that caught everyone's attention was the relatively small number of instruc-
tions available, typically around 50. This number was far smaller than the 200 to
300 on established computers such as the DEC VAX and the large IBM main-
frames. In fact, the acronym RISC stands for
Reduced Instruction Set Com-
puter
, which was contrasted with CISC, which stands for
Complex Instruction
Set Computer
(a thinly veiled reference to the VAX, which dominated university
