Hardware Reference
In-Depth Information
The next block contains instructions for sign extension, negation, logical com-
plement, increment and decrement. The sign extend operations have no explicit
operands, but act on the
DX
:
AX
or the
AH
:
AL
register combinations. The single
operand for the other operations of this group can be found at any effective
address. The flags are affected in the expected way in case of the
NEG
,
INC
and
DEC
, except that the carry is not affected in the increment and decrement, which is
quite unexpected and which some people regard as a design error.
The next block of instructions is the two-operand logical group, all of whose
instructions behave as expected. In the shift and rotate group, all operations have
an effective address as their destination, but the source is either the byte register
CL
or the number 1. In the shifts, all four flags are affected; in the rotates, only the
carry and the overflow are affected. The carry always gets the bit that is shifted or
rotated out of the high-order or low-order bit, depending on the direction of the
shift or rotate. In the rotates with carry,
RCR
,
RCL
,
RCRB
, and
RCLB
, the carry
together with the operand at the effective address, constitutes a 17-bit or a 9-bit cir-
cular shift register combination, which facilitates multiple word shifts and rotates.
The next block of instructions is used to manipulate the flag bits. The main
reason for doing this is to prepare for conditional jumps. The double arrow (
)is
used to indicate the two operands in compare and test operations, which do not
change during the operation. In the
TEST
operation, the logical
AND
of the
operands is computed to set or clear the zero flag and the sign flag. The computed
value itself is not stored anywhere and the operand is unmodified. In the
CMP
, the
difference of the operands is computed and all four flags are set or cleared as a
result of the comparison. The direction flag, which determines whether the
SI
and
DI
registers should be incremented or decremented in the string instructions, can be
set or cleared by
STD
and
CLD
, respectively.
The 8088 also has a
parity flag
and an
auxiliary carry flag
. The parity flag
gives the parity of the result (odd or even). The auxiliary flag checks whether
overflow was generated in the low (4-bit) nibble of the destination. There are also
instructions
LAHF
and
SAHF
, which copy the low-order byte of the flag register in
AH
, and vice versa. The overflow flag is in the high-order byte of the condition
code register and is not copied in these instructions. These instructions and flags
are mainly used for backward compatibility with the 8080 and 8085 processors.
←
The following block contains the instructions for looping. The
LOOP
instruc-
tion decrements the
CX
register and jumps back to the label indicated if the result is
positive. The instructions
LOOPZ
,
LOOPE
,
LOOPNZ
and
LOOPNE
also test the zero
flag to see whether the loop should be aborted before
CX
is 0.
