Hardware Reference
In-Depth Information
simulates shared memory at the page level, making it similar to a NUMA machine,
except with a much greater penalty for remote references.
Finally, at the highest level, and the most loosely coupled, are the grids. These
are systems in which entire organizations are hooked together over the Internet to
share compute power, data, and other resources.
PROBLEMS
1.
Intel x86 instructions can be as long as 17 bytes. Is the x86 a VLIW CPU?
2.
As process-design technology allows engineers to put ever more transistors on a chip,
Intel and AMD have chosen to increase the number of cores on each chip. Are there
any other feasible choices they could have made instead?
3.
What are the clipped values of 96,
−
9, 300, and 256 when the clipping range is 0-255?
4.
Are the following TriMedia instructions allowed, and if not, why not?
a. Integer add, integer subtract, load, floating add, load immediate
b. Integer subtract, integer multiply, load immediate, shift, shift
c. Load immediate, floating add, floating multiply, branch, load immediate
5.
Figure 8-7(d) and (e) show 12 cycles of instructions. For each one, tell what happens
in the following three cycles.
6.
On a particular CPU, an instruction that misses the level 1 cache but hits the level 2
cache takes
k
cycles in total. If multithreading is used to mask level 1 cache misses,
how many threads must be run at once using fine-grained multithreading to avoid dead
cycles?
7.
The NVIDIA Fermi GPU is similar in spirit to one of the architectures we studied in
Chap. 2. Which one?
8.
One morning, the queen bee of a certain beehive calls in all her worker bees and tells
them that today's assignment is to collect marigold nectar. The workers then fly off in
different directions looking for marigolds. Is this an SIMD or an MIMD system?
9.
During our discussion of memory consistency models, we said that a consistency
model is a kind of contract between the software and the memory. Why is such a con-
tract needed?
10.
Consider a multiprocessor using a shared bus. What happens if two processors try to
access the global memory at exactly the same instant?
11.
Consider a multiprocessor using a shared bus. What happens if three processors try to
access the global memory at exactly the same instant?
12.
Suppose that for technical reasons it is possible for a snooping cache to snoop only on
address lines, not on data lines. Would this change affect the write through protocol?
