Hardware Reference
In-Depth Information
CPU 1
CPU 2
CPU 3
Memory
CPU 1 reads block A
(a)
A
Exclusive
Bus
Cache
CPU 1
CPU 2
CPU 3
Memory
CPU 2 reads block A
(b)
A
Shared
Shared
Bus
CPU 1
CPU 2
CPU 3
Memory
CPU 2 writes block A
(c)
A
Modified
Bus
CPU 1
CPU 2
CPU 3
Memory
CPU 3 reads block A
(d)
A
A
Shared
Shared
Bus
CPU 1
CPU 2
CPU 3
Memory
CPU 2 writes block A
(e)
A
Modified
Bus
CPU 1
CPU 2
CPU 3
Memory
CPU 1 writes block A
(f)
A
Modified
Bus
Figure 8-28.
The MESI cache coherence protocol.
