Hardware Reference
In-Depth Information
data structures, whereas SDRAM holds the actual packets being processed. Mak-
ing the SRAM and SDRAM external to the network processor chip gives the board
designers the flexibility to determine how much of each to supply. In this way,
low-end boards with a single network line (e.g., for a PC or server) can be
equipped with a small amount of memory whereas a high-end board for a large
router can be equipped with much more.
Network processor chips are optimized for quickly processing large numbers
of incoming and outgoing packets. Millions of packets per second per network
line is the norm and a router could easily have half a dozen lines. The only way to
achieve such processing rates is to build network processors that are highly parallel
inside. Indeed, all network processors consist of multiple
PPE
s, variously called
Protocol/Programmable/Packet Processing Engines
. Each one consists of a
(possibly modified) RISC core and a small amount of internal memory for holding
the program and some variables.
The PPEs can be organized in two ways. The simplest organization is having
all the PPEs identical. When a packet arrives at the network processor, either an
incoming packet from a network line or an outgoing packet from the bus, it is
handed to an idle PPE for processing. If no PPE is idle, the packet is queued in the
on-board SDRAM until a PPE frees up. When this organization is used, the hori-
zontal connections shown between the PPEs in Fig. 8-16 do not exist because the
PPEs have no need to communicate with one another.
The other PPE organization is the pipeline. In this one, each PPE performs
one processing step and then feeds a pointer to its output packet to the next PPE in
the pipeline. In this way, the PPE pipeline acts very much like the CPU pipelines
we studied in Chap. 2.
In both organizations, the PPEs are completely pro-
grammable.
In advanced designs, the PPEs have multithreading, meaning that they have
multiple register sets and a hardware register indicating which one is currently in
use. This feature is used to run multiple programs at the same time by allowing a
program (i.e., thread) switch by just changing the ''current register set'' variable.
Most commonly, when a PPE stalls, for example, when it references the SDRAM
(which takes multiple clock cycles), it can instantaneously switch to a runnable
thread. In this manner, a PPE can achieve a high utilization even when frequently
blocking to access the SDRAM or perform some other slow external operation.
In addition to the PPEs, all network processors contain a control processor,
usually just a standard general-purpose RISC CPU, for performing all work not re-
lated to packet processing, such as updating the routing tables. Its program and
data are in the local on-chip memory. Furthermore, many network-processor chips
also contain one or more specialized processors for doing pattern matching or
other critical operations. These processors are really small ASICs that are good at
one simple operation, such as looking up a destination address in the routing table.
All the components of the network processor communicate over one or more on-
chip, parallel buses that run at multigigabit/sec speeds.
