Hardware Reference
In-Depth Information
need. On the other hand, this approach requires redesigning the chip and it does
not scale well much above two CPUs. In contrast, just putting two or more CPU
cores on the same chip is relatively easy to do.
We will discuss multiprocessors later in the chapter. While that discussion is
somewhat focused on multiprocessors built from single-CPU chips, much of it
applies to multi-CPU chips as well.
The Core i7 Single-Chip Multiprocessor
The Core i7 CPU is a single-chip multiprocessor that is manufactured with
four or more cores on a single silicon die. The high-level organization of a Core i7
processor is illustrated in Fig. 8-11.
IA-32
CPU+L1
IA-32
CPU + L1
IA-32
CPU + L1
IA-32
CPU+L1
L2 cache
L2 cache
L2 cache
L2 cache
Ring network
L3 shared cache
Figure 8-11. Single-chip multiprocessor architecture of the Core i7.
Each processor in the Core i7 has its own private L1 instruction and data caches,
plus its own private L2 unified cache. The processors are connected to the private
caches with dedicated point-to-point connections. The next level of the memory
hierarchy is the shared and unified L3 data cache.
The L2 caches connect to the L3 shared cache using a ring network . When a
communication request enters the ring network, it is forwarded to the next node on
the network, where it is checked to see if it has reached its destination node. This
process continues from node to node on the ring until the destination node is found
or the request arrives at its source again (in which case the destination does not
exist). The advantage of a ring network is it is a cheap way to get high bandwidth,
at the cost of increased latency as requests hop from node to node. The Core i7
ring network serves two primary purposes. First, it provides a way to move memo-
ry and I/O requests between the caches and processors. Second, it implements the
checks necessary to ensure that each processor is always seeing a coherent view of
memory. We will learn more about these coherence checks later in this chapter.
 
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