Hardware Reference
In-Depth Information
address space is broken up into pieces in a similar way, each piece being the same
size as a page, so that each piece of main memory is capable of holding exactly
one page. These pieces of main memory into which the pages go are called
page
frames
. In Fig. 6-2 the main memory contains only one page frame. In practical
designs it will usually contain thousands of them.
Figure 6-3(a) illustrates one possible way to divide up the first 64 KB of a vir-
tual address space—in 4-KB pages. (Note that we are talking about 64 KB and 4K
of addresses here. An address might be a byte but could equally well be a word on
a computer in which consecutive words had consecutive addresses.) The virtual
memory of Fig. 6-3 would be implemented by means of a page table with as many
entries as there are pages in the virtual address space. For simplicity, we have
shown only the first 16 entries here. When the program tries to reference a word in
the first 64 KB of its virtual address space, whether to fetch instructions, fetch
data, or store data, it first generates a virtual address between 0 and 65532 (assum-
ing that word addresses must be divisible by 4). Indexing, indirect addressing, and
all the usual techniques may be used to generate this address.
Figure 6-3(b) shows a physical memory consisting of eight 4-KB page frames.
This memory might be limited to 32 KB because (1) that is all the machine had (a
processor embedded in a washing machine or microwave oven might not need
more), or (2) the rest of the memory was allocated to other programs.
Now consider how a 32-bit virtual address can be mapped onto a physical
main-memory address. After all, the only thing the memory understands are main
memory addresses, not virtual addresses, so that is what it must be given. Every
computer with virtual memory has a device for doing the virtual-to-physical map-
ping. This device is called the
MMU
(
Memory Management Unit
). It may be
on the CPU chip, or it may be on a separate chip that works closely with the CPU
chip. Since our sample MMU maps from a 32-bit virtual address to a 15-bit physi-
cal address, it needs a 32-bit input register and a 15-bit output register.
To see how the MMU works, consider the example of Fig. 6-4. When the
MMU is presented with a 32-bit virtual address, it separates the address into a
20-bit virtual page number and a 12-bit offset within the page (because the pages
in our example are 4K). The virtual page number is used as an index into the page
table to find the entry for the page referenced. In Fig. 6-4, the virtual page number
is 3, so entry 3 of the page table is selected, as shown.
The first thing the MMU does with the page-table entry is check to see if the
page referenced is currently in main memory. After all, with 2
20
virtual pages and
only eight page frames, not all virtual pages can be in memory at once. The MMU
makes this check by examining the
present/absent bit
in the page-table entry. In
our example, the bit is 1, meaning the page is currently in memory.
The next step is to take the page-frame value from the selected entry (6 in this
case) and copy it into the upper 3 bits of the 15-bit output register. Three bits are
needed because there are eight page frames in physical memory. In parallel with
this operation, the low-order 12 bits of the virtual address (the page-offset field) are
