Hardware Reference
In-Depth Information
if (R1 == 0) {
CMP R1,0
CMOVZ R2,R3,R1
R2 = R3;
BNE L1
CMOVZ R4,R5,R1
R4 = R5;
MOV R2,R3
CMOVN R6,R7,R1
} else {
MOV R4.R5
CMOVN R8,R9,R1
R6 = R7;
BR L2
R8 = R9;
L1: MOV R6,R7
}
MOV R8,R9
L2:
(a)
(b)
(c)
Figure 5-49. (a) An if statement. (b) Generic assembly code for (a). (c) Condi-
tional execution.
Although simple, the example of Fig. 5-50 shows the basic idea of how predi-
cation can be used to eliminate branches. The CMPEQ instruction compares two
registers and sets the predicate register P4 to 1 if they are equal and to 0 if they are
different. It also sets a paired register, say, P5 , to the inverse condition. Now the
instructions for the if and then parts can be put after one another, each one condi-
tioned on some predicate register (shown in angle brackets). Arbitrary code can be
put here provided that each instruction is properly predicated.
if (R1 == R2)
CMP R1,R2
CMPEQ R1,R2,P4
R3 = R4 + R5;
BNE L1
<P4> ADD R3,R4,R5
else
MOV R3,R4
<P5> SUB R6,R4,R5
R6=R4
R5
ADD R3,R5
BR L2
L1: MOV R6,R4
SUB R6,R5
L2:
(a)
(b)
(c)
Figure 5-50. (a) An if statement. (b) Generic assembly code for (a). (c) Predi-
cated execution.
In the IA-64, this idea is taken to the extreme, with comparison instructions for
setting the predicate registers as well as arithmetic and other instructions whose ex-
ecution is dependent on some predicate register. Predicated instructions can be
stuffed into the pipeline in sequence, with no stalls and no problems. That is why
they are so useful.
The way predication really works on the IA-64 is that every instruction is ac-
tually executed. At the very end of the pipeline, when it is time to retire an instruc-
tion, a check is made to see if the predicate is true. If so, the instruction is retired
normally and its results are written back to the destination register. If the predicate
is false, no writeback is done so the instruction has no effect. Predication is dis-
cussed further in Dulong (1998).
 
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