Hardware Reference
In-Depth Information
Bits
41
41
41
5
Instruction 2
Instruction 1
Instruction 0
Template
Bits
10
7
7
7
6
4
OP. TYPE
REGISTER 3
REGISTER 2
REGISTER 1
OPERATION GROUP
PREDICATE REGISTER
Figure 5-47.
An IA-64 bundle contains three instructions.
plus another 216 to indicate an instruction-group marker after instruction 0, anoth-
er 216 to indicate an instruction-group marker after instruction 1, and yet another
216 to indicate an instruction-group marker after instruction 2. With only 5 bits
available, only a very limited number of these combinations are allowed. On the
other hand, allowing three floating-point instructions in a bundle would not work,
not even if there were a way to specify this, since the CPU cannot initiate three
floating-point instructions simultaneously. The allowed combinations are the ones
that are actually feasible.
Another important feature of the IA-64 is the new way it deals with conditional
branches. If there were a way to get rid of most of them, CPUs could be made
much simpler and faster. At first thought it might seem that getting rid of condi-
tional branches would be impossible because programs are full of
if
statements.
However, IA-64 uses a technique called
predication
that can greatly reduce their
number (August et al., 1998, and Hwu, 1998). We will now briefly describe it.
In traditional architectures, all instructions are unconditional in the sense that
when the CPU hits an instruction, it just carries the instruction out. There is no in-
ternal debate of the form: ''To do or not to do, that is the question.'' In contrast, in
a predicated architecture, instructions contain conditions (predicates) telling when
they should be executed and when not. This paradigm shift from unconditional in-
structions to predicated instructions is what allows us to get rid of (many) condi-
tional branches. Instead of having to make a choice between one sequence of
unconditional instructions or another sequence of unconditional instructions, all
the instructions are merged into a single sequence of predicated instructions, using
different predicates for different instructions.
