Hardware Reference
In-Depth Information
Instruction
Description
Semantics
ADD DST,SRC
Add
DST
←
DST + SRC
ADC DST,SRC
ADIW DST,IMM
SUB DST,SRC
SUBI DST,IMM
SBC DST,SRC
SBCI DST,IMM
SBIW DST,IMM
Add with Carry
Add Immediate to Word
Subtract
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
Logical AND with Immediate
Logical OR
Logical OR with Immediate
Exclusive OR
One's Complement
Two's Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Set Register
Multiply Unsigned
Multiply Signed
Multiply Signed with Unsigned
PC-relative Jump
Indirect Jump to Z
Jump
Relative Call
Indirect Call to (Z)
Call
Return
Compare
Compare with Carry
Compare with Immediate
Branch on Condition
Copy Register
Copy Register Pair
Load Immediate
Load Direct
Load Indirect
Load Indirect with Displacement
Store Direct
Store Indirect
Store Indirect with Displacement
Push Register on Stack
Pop Register from Stack
Logical Shift Left by One
Logical Shift Right by One
Rotate Left by One
Rotate Right by One
Arithmetic Shift Right by One
DST
←
DST+SRC+C
DST+1:DST
←
DST+1:DST + IMM
DST
←
DST - SRC
DST
←
DST - IMM
DST
←
DST-SRC-C
DST
←
DST-IMM-C
DST+1:DST
←
DST+1:DST - IMM
AND DST,SRC
DST
←
DST AND SRC
ANDI DST,IMM
DST
←
DST AND IMM
OR DST,SRC
DST
←
DST OR SRC
ORI DST,IMM
DST
←
DST OR IMM
EOR DST,SRC
DST
←
DST XOR SRC
COM DST
DST
←
0xFF - DST
NEG DST
DST
←
0x00 - DST
SBR DST,IMM
CBR DST,IMM
DST
DST OR IMM
DST
←
DST AND (0xFF - IMM)
DST
←
DST+1
DST
←
DST-1
DST
←
DST AND DST
DST
←
DST XOR DST
DST
←
0xFF
R1:R0
←
DST * SRC
R1:R0
←
DST * SRC
R1:R0
←
ING DST
DEC DST
TST DST
CLR DST
SER DST
MUL DST,SRC
MULS DST,SRC
MULSU DST,SRC
RJMP IMM
IJMP
JMP IMM
RCALL IMM
ICALL
CALL
RET
CP DST,SRC
CPC DST,SRC
CPI DST,IMM
BRcc IMM
MOV DST,SRC
MOVW DST,SRC
LDI DST,IMM
LDS DST,IMM
LD DST,XYZ
LDD DST,XYZ+IMM
STS IMM,SRC
ST XYZ,SRC
STD XYZ+IMM,SRC
PUSH REGLIST
POP REGLIST
LSL DST
LSR DST
ROL DST
ROR DST
ASR DST
←
DST * SRC
PC
←
PC+IMM+1
PC
←
Z (R30:R31)
PC
IMM
STACK
←
←
PC+2, PC
←
PC+IMM+1
STACK
←
PC+2, PC
←
Z (R30:R31)
STACK
←
PC+2, PC
←
IMM
PC
STACK
DST - SRC
DST-SRC-C
DST - IMM
if cc(true) PC
←
PC+IMM+1
DST
←
SRC
DST+1:DST
←
SRC+1:SRC
DST
←
IMM
DST
←
MEM[IMM]
DST
←
MEM[XYZ]
DST
←
MEM[XYZ+IMM]
MEM[IMM]
←
←
SRC
MEM[XYZ]
SRC
MEM[XYZ+IMM]
←
←
SRC
STACK
←
REGLIST
REGLIST
←
STACK
DST
←
DST LSL 1
DST
←
DST LSR 1
DST
←
DST ROL 1
DST
DST ROR 1
←
DST
←
DST ASR 1
SRS = source register
DST = destination register
IMM = immediate value
XYZ = X, Y, or Z register pair
MEM[A] = access memory at address A
Figure 5-35.
The ATmega168 AVR instruction set.
