Hardware Reference
In-Depth Information
branches on various conditions, but it also deposits the address of the next instruc-
tion in the link register (R14). This instruction is useful to implement procedure
calls. Unlike all other RISC architectures, there is no explicit branch to register ad-
dress instruction. This instruction can be easily synthesized by using a
MOV
in-
struction with the destination set to the program counter (R15).
Two ways are provided for calling procedures. The first
BLcc
instruction uses
the ''Branch'' format of Fig. 5-14 with a 24-bit PC-relative
word
offset. This value
is enough to reach any instruction within 32 megabytes of the called in either di-
rection. The second
BLcc
instruction jumps to the address in the specified register.
This can be used to implement dynamically bound procedure calls (e.g., C++ virtu-
al functions) or calls beyond the reach of 32 megabytes.
The last group contains some leftovers.
MOVT
is needed because there is no
way to get a 32-bit immediate operand into a register. The way it is done is to use
MOVT
to set bits 16 through 31 and then have the next instruction supply the re-
maining bits using the immediate format. The
MRS
and
MSR
instructions allow
reading and writing of the processor status word (
PSR
). The
SWP
instructions per-
form atomic swaps between a register and a memory location. These instruction
implement the multiprocessor synchronization primitives that we will learn about
in Chap. 8. Finally, the
SWI
instruction initiates a software interrupt, which is an
overly fancy way of saying that it initiates a system call.
The ATmega168 has a simple instruction set, shown in Fig. 5-35. Each line
gives the mnemonic, a brief description, and a snippet of pseudocode that details
the operation of the instruction. As is to be expected, there are a variety of
MOV
in-
structions for moving data between the registers. There are instructions for push-
ing and popping from a stack, which is pointed to by the 16-bit stack pointer (SP)
in memory. Memory can be accessed with either an immediate address, register
indirect, or register indirect plus a displacement. To allow up to 64 KB of ad-
dressing, the load with an immediate address is a 32-bit instruction. The indirect
addressing modes utilize the X, Y, and Z register pairs, which combine two 8-bit
registers to form a single 16-bit pointer.
The ATmega168 has simple arithmetic instructions for adding, subtracting, and
multiplying, the latter of which use two registers. Incrementing and decrementing
are also possible and commonly used. Boolean, shift, and rotate instructions are
also present. The branch and call instruction can target an immediate address, a
PC-relative address, or an address contained in the Z register pair.
The three example instruction sets are very different. The Core i7 is a classic
two-address 32-bit CISC machine, with a long history, peculiar and highly irregu-
lar addressing modes, and many instructions that reference memory.
