Hardware Reference
In-Depth Information
way, arbitrary blocks of data can be moved, compared, and so on. The next group
manages the condition codes.
The last group is a hodge-podge of instructions that do not fit in anywhere else.
These include conversions, stack frame management, stopping the CPU, and I/O.
The Core i7 has a number of
prefixes
, of which we have already mentioned
one (
REP
). Each of these prefixes is a special byte that can precede most instruc-
tions, analogous to
WIDE
in IJVM.
REP
causes the instruction following it to be re-
peated until
ECX
hits 0, as mentioned above.
REPZ
and
REPNZ
repeatedly execute
the following instruction until the
Z
condition code is set, or not set, respectively.
LOCK
reserves the bus for the entire instruction, to permit multiprocessor synchron-
ization. Other prefixes are used to force an instruction to operate in 16-bit mode,
or in 32-bit mode, which not only changes the length of the operands but also com-
pletely redefines the addressing modes. Finally, the Core i7 has a complex seg-
mentation scheme with code, data, stack, and extra segments, a holdover from the
8088. Prefixes are provided to force memory references to use specific segments,
but these will not be of concern to us (fortunately).
Nearly all of the user-mode integer ARM instructions that a compiler might
generate are listed in Fig. 5-34. Floating-point instructions are not given here, nor
are control instructions (e.g., cache management, system reset), instructions involv-
ing address spaces other than the user's, or instruction extensions such as Thumb.
The set is surprisingly small: the OMAP4430 ARM ISA really is a reduced in-
struction set computer.
The
LDR
and
STR
instructions are straightforward, with versions for 1, 2, and 4
bytes. When a number less than 32 bits is loaded into a (32-bit) register, the num-
ber can be either sign extended or zero extended. Instructions for both exist.
The next group is for arithmetic, which can optionally set the processor status
register's condition code bits. On CISC machines, most instructions set the condi-
tion codes, but on a RISC machine that is undesirable because it restricts the com-
piler's freedom to move instructions around when trying to schedule them to toler-
ate instruction delays. If the original instruction order is A ... B ... C with A setting
the condition codes and B testing them, the compiler cannot insert C between A
and B if C sets the condition codes. For this reason, two versions of many instruc-
tions are provided, with the compiler normally using the one that does not set the
condition codes, unless it is planning to test them later. The programmer specifies
the setting of the condition codes by adding an ''S'' to the end of the instruction
opcode name, for example,
ADDS
. A bit in the instruction indicates to the processor
that the condition codes should be set. Multiplication and multiply-accumulate are
also supported.
The shift group contains one left shift and two right shifts, each of which oper-
ate on 32-bit registers. The rotate right instruction does a circular rotation of bits
