Hardware Reference
In-Depth Information
public static void output buffer(char buf[ ], int count) {
// Output a block of data to the device
int status, i, ready;
for (i = 0; i < count; i++) {
do {
status = in(display status reg);
// get status
ready = (status >> 7) & 0x01;
// isolate ready bit
} while (ready != 1);
out(display buffer reg, buf[i]);
}
}
Figure 5-31.
An example of programmed I/O.
this is done. By setting the
INTERRUPT ENABLE
bit in a device register, the soft-
ware can request that the hardware give it a signal when the I/O is completed. We
will study interrupts in detail later in this chapter when we come to flow of control.
It is worth mentioning that in many computers, the interrupt signal is generated
by ANDing the
INTERRUPT ENABLE
bit with the
READY
bit. If the software first
enables interrupts (before starting I/O), an interrupt will happen immediately, be-
cause the
READY
bit will be 1. Thus it may be necessary to first start the device,
then immediately afterward enable interrupts. Writing a byte to the status register
does not change the
READY
bit, which is read only.
Although interrupt-driven I/O is a big step forward compared to programmed
I/O, it is far from perfect. The problem is that an interrupt is required for every
character transmitted. Processing an interrupt is expensive. A way is needed to get
rid of most of the interrupts.
The solution lies in going back to programmed I/O, but having somebody else
do it. (The solution to many problems lies in having somebody else do the work.)
Figure 5-32 shows how this is arranged. Here we have added a new chip, a
DMA
(
Direct Memory Access
) controller to the system, with direct access to the bus.
The DMA chip has (at least) four registers inside it, all of which can be loaded
by software running on the CPU. The first contains the memory address to be read
or written. The second contains the count of how many bytes (or words) are to be
transferred. The third specifies the device number or I/O space address to use, thus
specifying which I/O device is desired. The fourth tells whether data are to be read
from or written to the I/O device.
To write a block of 32 bytes from memory address 100 to a terminal (say, de-
vice 4), the CPU writes the numbers 32, 100, and 4 into the first three DMA regis-
ters, and then the code for
WRITE
(say, 1) in the fourth one, as illustrated in
Fig. 5-32. Once initialized like this, the DMA controller makes a bus request to
read byte 100 from the memory, the same way the CPU would read from the mem-
ory. Having gotten this byte, the DMA controller then makes an I/O request to de-
vice 4 to write the byte to it. After both of these operations have been completed,
