Hardware Reference
In-Depth Information
the processor can consume them. Each memory has a bandwidth that is determin-
ed by its technology and engineering design. The bandwidth bottleneck applies
not only to the main memory but also to all the caches.
If the bandwidth of an instruction cache is
t
bps and the average instruction
length is
r
bits, the cache can deliver at most
t
/
r
instructions per second. Notice
that this is an
upper limit
on the rate at which the processor can execute instruc-
tions, though there are current research efforts to breach even this seemingly insur-
mountable barrier. Clearly, the rate at which instructions can be executed (i.e., the
processor speed) may be limited by the instruction length. Shorter instructions
means a faster processor. Since modern processors can execute multiple instruc-
tions every clock cycle, fetching multiple instructions per clock cycle is imperative.
This aspect of the instruction cache makes the size of instructions an important de-
sign criterion that has major implications for performance.
A second design criterion is sufficient room in the instruction format to express
all the operations desired. A machine with 2
n
operations with all instructions
smaller than
n
bits is impossible. There simply will not be enough room in the op-
code to indicate which instruction is needed. And history has shown over and over
the folly of not leaving a substantial number of opcodes free for future additions to
the instruction set.
A third criterion concerns the number of bits in an address field. Consider the
design of a machine with an 8-bit character and a main memory that must hold 2
32
characters. The designers could choose to assign consecutive addresses to units of
8, 16, 24, or 32 bits, as well as other possibilities.
Imagine what would happen if the design team degenerated into two warring
factions, one advocating making the 8-bit byte the basic unit of memory, and the
other advocating the 32-bit word. The former group would propose a memory of
2
32
bytes, numbered 0, 1, 2, 3, ..., 4,294,967,295. The latter group would propose
a memory of 2
30
words numbered 0, 1, 2, 3, ..., 1,073,741,823.
The first group would point out that in order to compare two characters in the
32-bit word organization, the program would not only have to fetch the words con-
taining the characters but would also have to extract each character from its word
in order to compare them. Doing so costs extra instructions and therefore wastes
space. The 8-bit organization, on the other hand, provides an address for every
character, thus making the comparison much easier.
The 32-bit word supporters would retaliate by pointing out that their proposal
requires only 2
30
separate addresses, giving an address length of only 30 bits,
whereas the 8-bit byte proposal requires 32 bits to address the same memory. A
shorter address means a shorter instruction, which not only takes up less space but
also requires less time to fetch. Alternatively, they could retain the 32-bit address
to reference a 16-GB memory instead of a puny 4-GB memory.
This example demonstrates that in order to gain a finer memory resolution, one
must pay the price of longer addresses and thus longer instructions. The ultimate
in resolution is a memory organization in which every bit is directly addressable
