Hardware Reference
In-Depth Information
1 Word
1 Word
1 Word
Instruction
Instruction
Instruction
Instruction
Instruction
Instruction
Instruction
Instruction
Instruction
Instruction
Instruction
Instruction
Instr.
Instr.
Instruction
Instruction
Instruction
(a)
(b)
(c)
Figure 5-10.
Some possible relationships between instruction and word length.
new instructions and exploit other opportunities that arise over an extended period
is of great importance, but only if the architecture—and the company building it—
survive long enough for the architecture to be a success.
The efficiency of a particular ISA is highly dependent on the technology with
which the computer is to be implemented. Over a long period of time, this tech-
nology will undergo vast changes, and some of the ISA choices will be seen (with
20/20 hindsight) as unfortunate. For example, if memory accesses are fast, a stack-
based design (like IJVM) is a good one, but if they are slow, then having many reg-
isters (like the OMAP4430 ARM CPU) is the way to go. Readers who think this
choice is easy are invited to find a slip of paper and write down their predictions
for (1) a typical CPU clock speed, and (2) a typical RAM access time for com-
puters 20 years in the future. Fold this slip neatly and keep it for 20 years. Then
unfold and read it. The humility-challenged can forget the slip of paper and just
post their predictions to the Internet now.
Of course, even far-sighted designers may not be able to make all the right
choices. And even if they could, they have to deal with the short term, too. If this
elegant ISA is a little more expensive than its current ugly competitors, the com-
pany may not survive long enough for the world to appreciate the elegance of the
ISA.
All things being equal, short instructions are better than long ones. A program
consisting of
n
16-bit instructions takes up only half as much memory space as
n
32-bit instructions. With ever-declining memory prices, this factor might be less
important in the future, were it not for the fact that software is metastasizing even
faster than memory prices are dropping.
Furthermore, minimizing the size of the instructions may make them harder to
decode or harder to overlap. Therefore, achieving the minimum instruction size
must be weighed against the time required to decode and execute the instructions.
Another reason for minimizing instruction length is already important and
becoming more so with faster processors: memory bandwidth (the number of
bits/sec the memory is capable of supplying). The impressive growth in processor
speeds over the last few decades has not been matched by equal increases in mem-
ory bandwidth. An increasingly common constraint on processors stems from the
inability of the memory system to supply instructions and operands as rapidly as
